Home
last modified time | relevance | path

Searched +full:0 +full:x8000 (Results 1076 – 1100 of 1886) sorted by relevance

1...<<41424344454647484950>>...76

/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
[all...]
/linux/drivers/ata/
H A Dpata_sis.c56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
58 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
60 { 0, }
[all...]
/linux/drivers/scsi/
H A Dzorro_esp.c60 unsigned char dma_addr; /* DMA address [0x0000] */
61 unsigned char dmapad2[0x7fff];
62 unsigned char dma_latch; /* DMA latch [0x8000] */
68 unsigned char dma_addr; /* DMA address [0x0000] */
69 unsigned char dmapad2[0xf];
70 unsigned char dma_latch; /* DMA latch [0x0010] */
76 unsigned char dma_led_ctrl; /* DMA led control [0x000] */
77 unsigned char dmapad1[0x0f];
78 unsigned char dma_addr0; /* DMA address (MSB) [0x01
[all...]
/linux/drivers/comedi/drivers/
H A Djr3_pci.h40 * channels. Channel 0 shows the excitation voltage at the sensor. It
86 * value of 0x0001 and the V2z bit corresponds to a hex value of
87 * 0x0020. Example: to specify the axes V1x, V1y, V2x, and V2z the
88 * pattern would be 0x002b. Vector 1 defaults to a force vector and
98 fx = 0x0001,
99 fy = 0x0002,
100 fz = 0x0004,
101 mx = 0x0008,
102 my = 0x0010,
103 mz = 0x002
[all...]
/linux/drivers/misc/keba/
H A Dcp500.c24 #define PCI_VENDOR_ID_KEBA 0xCEBA
25 #define PCI_DEVICE_ID_KEBA_CP035 0x2706
26 #define PCI_DEVICE_ID_KEBA_CP505 0x2703
27 #define PCI_DEVICE_ID_KEBA_CP520 0x2696
29 #define CP500_SYS_BAR 0
32 /* BAR 0 registers */
33 #define CP500_VERSION_REG 0x00
34 #define CP500_RECONFIG_REG 0x11 /* upper 8-bits of STARTUP register */
35 #define CP500_PRESENT_REG 0x20
36 #define CP500_AXI_REG 0x4
[all...]
/linux/arch/arm/common/
H A Dlocomo.c32 #define IRQ_LOCOMO_KEY (0)
39 /* 0 : CH.1 , 1 : CH. 2 */
41 #define M62332_SLAVE_ADDR 0x4e /* Slave address */
42 #define M62332_W_BIT 0x00 /* W bit (0 only) */
43 #define M62332_SUB_ADDR 0x00 /* Sub address */
44 #define M62332_A_BIT 0x00 /* A bit (0 only) */
127 .offset = 0,
128 .length = 0,
[all...]
/linux/drivers/pci/controller/
H A Dpcie-brcmstb.c39 #define BRCM_PCIE_CAP_REGS 0x00ac
42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
43 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
44 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
46 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
47 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
49 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
50 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK 0x1f0
51 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
53 #define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f
[all...]
/linux/drivers/scsi/bnx2fc/
H A Dbnx2fc_tgt.c68 timer_setup(&tgt->ofld_timer, bnx2fc_ofld_timer, 0); in bnx2fc_ofld_wait()
88 int i = 0; in bnx2fc_offload_session()
169 int i = 0; in bnx2fc_flush_active_ios()
179 io_req->on_active_queue = 0; in bnx2fc_flush_active_ios()
199 bnx2fc_process_cleanup_compl(io_req, io_req->task, 0); in bnx2fc_flush_active_ios()
209 io_req->on_tmf_queue = 0; in bnx2fc_flush_active_ios()
218 io_req->on_active_queue = 0; in bnx2fc_flush_active_ios()
233 bnx2fc_process_cleanup_compl(io_req, io_req->task, 0); in bnx2fc_flush_active_ios()
262 i = 0; in bnx2fc_flush_active_ios()
264 /* wait for active_ios to go to 0 */ in bnx2fc_flush_active_ios()
[all...]
/linux/sound/isa/sb/
H A Demu8000.c100 unsigned right_bit = (mode & EMU8000_RAM_RIGHT) ? 0x01000000 : 0; in snd_emu8000_dma_chan()
103 EMU8000_CCCA_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
104 EMU8000_DCYSUSV_WRITE(emu, ch, 0x807F); in snd_emu8000_dma_chan()
107 EMU8000_DCYSUSV_WRITE(emu, ch, 0x80); in snd_emu8000_dma_chan()
108 EMU8000_VTFT_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
109 EMU8000_CVCF_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
110 EMU8000_PTRX_WRITE(emu, ch, 0x40000000); in snd_emu8000_dma_chan()
111 EMU8000_CPF_WRITE(emu, ch, 0x40000000); in snd_emu8000_dma_chan()
112 EMU8000_PSST_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
[all...]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c33 #define COMPHY_LANE2_INDIR_ADDR 0x0
34 #define COMPHY_LANE2_INDIR_DATA 0x4
37 #define COMPHY_LANE2_REGS_BASE 0x200
43 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
46 #define COMPHY_POWER_PLL_CTRL 0x01
55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
56 #define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1)
57 #define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
58 #define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4)
59 #define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x
[all...]
/linux/drivers/net/ethernet/freescale/
H A Dgianfar.h70 #define MAX_TX_QS 0x8
71 #define MAX_RX_QS 0x8
74 #define MAXGROUPS 0x2
99 #define DEFAULT_FIFO_TX_THR 0x100
100 #define DEFAULT_FIFO_TX_STARVE 0x40
101 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
126 #define DEFAULT_RX_COALESCE 0
127 #define DEFAULT_RXCOUNT 0
130 #define MII_TBICON 0x11
133 #define TBICON_CLK_SELECT 0x002
[all...]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101.dtsi34 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0000>;
84 reg = <0x0100>;
94 reg = <0x0200>;
104 reg = <0x0300>;
114 reg = <0x0400>;
124 reg = <0x0500>;
134 reg = <0x0600>;
144 reg = <0x070
[all...]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 cpu0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x
[all...]
/linux/sound/hda/codecs/helpers/
H A Dhp_x360.c10 { 0x17, 0x90170110 }, in alc295_fixup_hp_top_speakers()
14 WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0000), WRITE_COEF(0x28, 0x0000), WRITE_COEF(0x29, 0xb02 in alc295_fixup_hp_top_speakers()
[all...]
/linux/arch/mips/boot/dts/loongson/
H A Dls7a-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x2000000
[all...]
/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-reg.h12 #define ADDR_IMEM 0x10000
13 #define ADDR_DMEM 0x20000
16 #define APB_CTRL 0
17 #define XT_INT_CTRL 0x04
18 #define MAILBOX_FULL_ADDR 0x08
19 #define MAILBOX_EMPTY_ADDR 0x0c
20 #define MAILBOX0_WR_DATA 0x10
21 #define MAILBOX0_RD_DATA 0x14
22 #define KEEP_ALIVE 0x18
23 #define VER_L 0x1
[all...]
/linux/arch/powerpc/boot/dts/
H A Dmpc832x_rdb.dts26 #size-cells = <0>;
28 PowerPC,8323@0 {
30 reg = <0x0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x04000000>;
51 ranges = <0x0 0xe0000000 0x00100000>;
[all …]
H A Dbluestone.dts16 dcr-parent = <&{/cpus/cpu@0}>;
26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
[all...]
H A Dmpc8349emitx.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; // from bootloader
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7362.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x41140
[all...]
H A Dbcm7360.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
25 #address-cells = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
51 ranges = <0 0x10000000 0x01000000>;
55 reg = <0x41140
[all...]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_5_1_sc8180x.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c
[all...]
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c
[all...]
H A Ddpu_6_0_sm8250.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c
[all...]
/linux/drivers/clk/qcom/
H A Dvideocc-sm8450.c34 { 249600000, 2020000000, 0 },
39 .l = 0x0044001e,
40 .alpha = 0x0,
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00182261,
43 .config_ctl_hi1_val = 0x32aa299c,
44 .user_ctl_val = 0x00000000,
45 .user_ctl_hi_val = 0x00000805,
50 .l = 0x1e,
51 .alpha = 0x
[all...]

1...<<41424344454647484950>>...76