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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
183 reg = <0x0 0xc000000 0x0 0x4000000>;
184 #address-cells = <0>;
188 <&cpu0_intc 0xffffffff>,
189 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
190 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
191 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
[all …]
/linux/drivers/media/spi/
H A Dgs1662.c26 #define REG_STATUS 0x04
27 #define REG_FORCE_FMT 0x06
28 #define REG_LINES_PER_FRAME 0x12
29 #define REG_WORDS_PER_LINE 0x13
30 #define REG_WORDS_PER_ACT_LINE 0x14
31 #define REG_ACT_LINES_PER_FRAME 0x15
33 #define MASK_H_LOCK 0x001
34 #define MASK_V_LOCK 0x002
35 #define MASK_STD_LOCK 0x004
36 #define MASK_FORCE_STD 0x020
[all …]
/linux/drivers/net/ethernet/dec/tulip/
H A D21142.c21 static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, };
22 u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, };
23 static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
36 int new_csr6 = 0; in t21142_media_task()
40 if ((csr14 & 0x80) && (csr12 & 0x7000) != 0x5000) in t21142_media_task()
46 if (tulip_check_duplex(dev) < 0) { in t21142_media_task()
70 } else if ((csr12 & 0x7000) != 0x5000) { in t21142_media_task()
77 new_csr6 = 0x82420000; in t21142_media_task()
78 dev->if_port = 0; in t21142_media_task()
79 iowrite32(0, ioaddr + CSR13); in t21142_media_task()
[all …]
/linux/fs/smb/server/
H A Dsmb_common.h19 #define SMB1_PROT 0
27 #define BAD_PROT 0xFFFF
41 #define MAX_STREAM_PROT_LEN 0x00FFFFFF
44 #define F_SUPERSEDED 0
52 #define ATTR_POSIX_SEMANTICS 0x01000000
53 #define ATTR_BACKUP_SEMANTICS 0x02000000
54 #define ATTR_DELETE_ON_CLOSE 0x04000000
55 #define ATTR_SEQUENTIAL_SCAN 0x08000000
56 #define ATTR_RANDOM_ACCESS 0x10000000
57 #define ATTR_NO_BUFFERING 0x20000000
[all …]
/linux/Documentation/firmware-guide/acpi/apei/
H A Deinj.rst13 ACPI: EINJ 0x000000007370A000 000150 (v01 INTEL 00000001 INTL 00000001)
50 0x00000001 Processor Correctable
51 0x00000002 Processor Uncorrectable non-fatal
52 0x00000004 Processor Uncorrectable fatal
53 0x00000008 Memory Correctable
54 0x00000010 Memory Uncorrectable non-fatal
55 0x00000020 Memory Uncorrectable fatal
56 0x00000040 PCI Express Correctable
57 0x00000080 PCI Express Uncorrectable non-fatal
58 0x00000100 PCI Express Uncorrectable fatal
[all …]
/linux/drivers/usb/host/
H A Dehci-orion.c26 #define USB_CMD 0x140
27 #define USB_CMD_RUN BIT(0)
29 #define USB_MODE 0x1a8
30 #define USB_MODE_MASK GENMASK(1, 0)
31 #define USB_MODE_DEVICE 0x2
32 #define USB_MODE_HOST 0x3
34 #define USB_CAUSE 0x310
35 #define USB_MASK 0x314
36 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
37 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
[all …]
/linux/drivers/hwmon/
H A Dmax6621.c24 #define MAX6621_TEMP_S0D0_REG 0x00
25 #define MAX6621_TEMP_S0D1_REG 0x01
26 #define MAX6621_TEMP_S1D0_REG 0x02
27 #define MAX6621_TEMP_S1D1_REG 0x03
28 #define MAX6621_TEMP_S2D0_REG 0x04
29 #define MAX6621_TEMP_S2D1_REG 0x05
30 #define MAX6621_TEMP_S3D0_REG 0x06
31 #define MAX6621_TEMP_S3D1_REG 0x07
32 #define MAX6621_TEMP_MAX_REG 0x08
33 #define MAX6621_TEMP_MAX_ADDR_REG 0x0a
[all …]
H A Dtmp108.c24 #define TMP108_REG_TEMP 0x00
25 #define TMP108_REG_CONF 0x01
26 #define TMP108_REG_TLOW 0x02
27 #define TMP108_REG_THIGH 0x03
35 #define TMP108_CONF_M0 0x0100 /* Sensor mode. */
36 #define TMP108_CONF_M1 0x0200
37 #define TMP108_CONF_TM 0x0400 /* Thermostat mode. */
38 #define TMP108_CONF_FL 0x0800 /* Watchdog flag - TLOW */
39 #define TMP108_CONF_FH 0x1000 /* Watchdog flag - THIGH */
40 #define TMP108_CONF_CR0 0x2000 /* Conversion rate. */
[all …]
H A Dgsc-hwmon.c66 ret = regs[0] | regs[1] << 8; in pwm_auto_point_temp_show()
84 temp = clamp_val(temp, 0, 100000); in pwm_auto_point_temp_store()
87 regs[0] = temp & 0xff; in pwm_auto_point_temp_store()
88 regs[1] = (temp >> 8) & 0xff; in pwm_auto_point_temp_store()
105 static SENSOR_DEVICE_ATTR_RO(pwm1_auto_point1_pwm, pwm_auto_point_pwm, 0);
106 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_temp, pwm_auto_point_temp, 0);
173 tmp = 0; in gsc_hwmon_read()
174 while (sz-- > 0) in gsc_hwmon_read()
179 if (tmp > 0x8000) in gsc_hwmon_read()
180 tmp -= 0xffff; in gsc_hwmon_read()
[all …]
/linux/arch/sparc/kernel/
H A Dsun4d_smp.c35 __asm__ __volatile__("swap [%1], %0\n\t" : in sun4d_swap()
37 "0" (val), "1" (ptr)); in sun4d_swap()
47 cpuid &= 0x1e; in show_leds()
48 __asm__ __volatile__ ("stba %0, [%1] %2" : : in show_leds()
59 cpu_leds[cpuid] = 0x6; in sun4d_cpu_pre_starting()
63 cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000); in sun4d_cpu_pre_starting()
89 __asm__ __volatile__("ld [%0], %%g6\n\t" in sun4d_cpu_pre_online()
93 cpu_leds[cpuid] = 0x9; in sun4d_cpu_pre_online()
107 cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */ in sun4d_cpu_pre_online()
118 current_set[0] = NULL; in smp4d_boot_cpus()
[all …]
/linux/arch/m68k/include/asm/
H A Damigahw.h209 #define DMAF_SETCLR (0x8000)
210 #define DMAF_AUD0 (0x0001)
211 #define DMAF_AUD1 (0x0002)
212 #define DMAF_AUD2 (0x0004)
213 #define DMAF_AUD3 (0x0008)
214 #define DMAF_DISK (0x0010)
215 #define DMAF_SPRITE (0x0020)
216 #define DMAF_BLITTER (0x0040)
217 #define DMAF_COPPER (0x0080)
218 #define DMAF_RASTER (0x0100)
[all …]
/linux/arch/powerpc/kernel/
H A Dmodule_32.c29 _count_relocs = 0; in count_relocs()
30 r_info = 0; in count_relocs()
31 r_addend = 0; in count_relocs()
32 for (i = 0; i < num; i++) in count_relocs()
68 return 0; in relacmp()
78 unsigned long ret = 0; in get_plt_size()
128 for (i = 0; i < hdr->e_shnum; i++) { in module_frob_arch_sections()
129 if (strcmp(secstrings + sechdrs[i].sh_name, ".init.plt") == 0) in module_frob_arch_sections()
131 else if (strcmp(secstrings + sechdrs[i].sh_name, ".plt") == 0) in module_frob_arch_sections()
141 = get_plt_size(hdr, sechdrs, secstrings, 0); in module_frob_arch_sections()
[all …]
/linux/drivers/net/ethernet/8390/
H A Dxsurf100.c10 ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x64, 0)
12 #define XS100_IRQSTATUS_BASE 0x40
13 #define XS100_8390_BASE 0x800
18 #define XS100_8390_DATA32_BASE 0x8000
19 #define XS100_8390_DATA32_SIZE 0x2000
21 #define XS100_8390_DATA_READ32_BASE 0x0880
22 #define XS100_8390_DATA_WRITE32_BASE 0x0C80
23 #define XS100_8390_DATA_AREA_SIZE 0x80
46 #define NE_CMD EI_SHIFT(0x00)
47 #define NE_RESET EI_SHIFT(0x1f)
[all …]
/linux/sound/core/oss/
H A Dmulaw.c29 #define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
30 #define QUANT_MASK (0xf) /* Quantization field mask. */
33 #define SEG_MASK (0x70) /* Segment field mask. */
37 int r = 0; in val_seg()
39 if (val & 0xf0) { in val_seg()
43 if (val & 0x0c) { in val_seg()
47 if (val & 0x02) in val_seg()
52 #define BIAS (0x84) /* Bias for linear code. */
58 * is biased by adding 33 which shifts the encoding range from (0 - 8158) to
74 * of leading 0's. The quantization interval is directly available as the
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-uniphier-ep.c23 #define PCL_RSTCTRL0 0x0010
27 #define PCL_RSTCTRL_PIPE3 BIT(0)
29 #define PCL_RSTCTRL1 0x0020
30 #define PCL_RSTCTRL_PERST BIT(0)
32 #define PCL_RSTCTRL2 0x0024
33 #define PCL_RSTCTRL_PHY_RESET BIT(0)
35 #define PCL_PINCTRL0 0x002c
41 #define PCL_PERST_OUT_REGVAL BIT(0)
43 #define PCL_PIPEMON 0x0044
46 #define PCL_MODE 0x8000
[all …]
/linux/arch/alpha/kernel/
H A Dsys_takara.c41 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); in takara_update_irq_hw()
42 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); in takara_update_irq_hw()
43 outl(mask & 0xffff0000UL, regaddr); in takara_update_irq_hw()
77 * The PALcode will have passed us vectors 0x800 or 0x810, in takara_device_interrupt()
92 intstatus = inw(0x500) & 15; in takara_device_interrupt()
102 if (intstatus & 1) handle_irq(16+0); in takara_device_interrupt()
111 int irq = (vector - 0x800) >> 4; in takara_srm_device_interrupt()
125 unsigned int ctlreg = inl(0x500); in takara_init_irq()
128 ctlreg &= ~0x8000; in takara_init_irq()
129 outl(ctlreg, 0x500); in takara_init_irq()
[all …]
/linux/drivers/crypto/
H A Dhifn_795x.c34 #define ACRYPTO_OP_DECRYPT 0
39 #define ACRYPTO_MODE_ECB 0
44 #define ACRYPTO_TYPE_AES_128 0
50 #define PCI_VENDOR_ID_HIFN 0x13A3
51 #define PCI_DEVICE_ID_HIFN_7955 0x0020
52 #define PCI_DEVICE_ID_HIFN_7956 0x001d
56 #define HIFN_BAR0_SIZE 0x1000
57 #define HIFN_BAR1_SIZE 0x2000
58 #define HIFN_BAR2_SIZE 0x8000
62 #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
[all …]
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dspectrum_nve_vxlan.c106 if (cfg->ttl == 0) { in mlxsw_sp_nve_vxlan_can_offload()
107 NL_SET_ERR_MSG_MOD(extack, "VxLAN: TTL must not be configured to 0"); in mlxsw_sp_nve_vxlan_can_offload()
111 if (cfg->label != 0) { in mlxsw_sp_nve_vxlan_can_offload()
112 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Flow label must be configured to 0"); in mlxsw_sp_nve_vxlan_can_offload()
157 config->learning_en = cfg->flags & VXLAN_F_LEARN ? 1 : 0; in mlxsw_sp_nve_vxlan_config()
172 /* VxLAN driver's default UDP source port range is 32768 (0x8000) in mlxsw_sp_nve_vxlan_config_prepare()
173 * to 60999 (0xee47). Set the upper 8 bits of the UDP source port in mlxsw_sp_nve_vxlan_config_prepare()
174 * to a random number between 0x80 and 0xee in mlxsw_sp_nve_vxlan_config_prepare()
177 udp_sport = (udp_sport % (0xee - 0x80 + 1)) + 0x80; in mlxsw_sp_nve_vxlan_config_prepare()
217 mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, false, 0); in mlxsw_sp1_nve_vxlan_config_clear()
[all …]
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xxfb_accel.c28 u32 total = 0; in mb862xxfb_write_fifo()
45 cmd[0] = (GDC_TYPE_SETREGISTER << 24) | (1 << 16) | GDC_REG_MODE_BITMAP; in mb86290fb_copyarea()
79 cmd[0] = (GDC_TYPE_SETREGISTER << 24) | (1 << 16) | GDC_REG_MODE_BITMAP; in mb86290fb_imageblit1()
89 i = 0; in mb86290fb_imageblit1()
103 int k = 0; in mb86290fb_imageblit1()
104 for (k = 0; k < step; k++) in mb86290fb_imageblit1()
127 cmd[0] = (GDC_TYPE_DRAWBITMAPP << 24) | in mb86290fb_imageblit8()
132 i = 0; in mb86290fb_imageblit8()
138 for (j = 0; j < step; j++) { in mb86290fb_imageblit8()
140 (((u32 *) (info->pseudo_palette))[*ptr]) & 0xffff; in mb86290fb_imageblit8()
[all …]
/linux/sound/hda/codecs/cirrus/
H A Dcs8409-tables.c24 .index = 0,
37 .index = 0,
62 { CS8409_PIN_AFG, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 }, /* WAKE from GPIO 3,4 */
63 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */
64 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
65 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */
66 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
67 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */
72 { CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 }, /* ASP-1-TX */
73 { CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 }, /* ASP-1-RX */
[all …]
/linux/drivers/net/ethernet/
H A Djme.h19 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
20 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
38 if (0) \
40 } while (0)
46 #define PCI_DCSR_MRRS 0x59
47 #define PCI_DCSR_MRRS_MASK 0x70
50 MRRS_128B = 0x00,
51 MRRS_256B = 0x10,
52 MRRS_512B = 0x20,
53 MRRS_1024B = 0x30,
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
15 ranges = <0 0x0 0x2a820000 0x20000>;
20 reg = <0x10000 0x10000>;
26 reg = <0x0 0x2b1f0000 0x0 0x1000>;
37 reg = <0x0 0x2b400000 0x0 0x10000>;
49 reg = <0x0 0x2b500000 0x0 0x10000>;
60 reg = <0x0 0x2b600000 0x0 0x10000>;
66 power-domains = <&scpi_devpd 0>;
71 reg = <0x0 0x2c010000 0 0x1000>,
72 <0x0 0x2c02f000 0 0x2000>,
[all …]
/linux/sound/soc/codecs/
H A Drt1015.c39 { 0x0000, 0x0000 },
40 { 0x0004, 0xa000 },
41 { 0x0006, 0x0003 },
42 { 0x000a, 0x081e },
43 { 0x000c, 0x0006 },
44 { 0x000e, 0x0000 },
45 { 0x0010, 0x0000 },
46 { 0x0012, 0x0000 },
47 { 0x0014, 0x0000 },
48 { 0x0016, 0x0000 },
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-j742s2-mcu-wakeup-common.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
49 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
48 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]

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