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/src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
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H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
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H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
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H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
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H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
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/src/sys/arm/include/
H A Dpl310.h37 #define PL310_CACHE_ID 0x000
38 #define CACHE_ID_RELEASE_SHIFT 0
39 #define CACHE_ID_RELEASE_MASK 0x3f
40 #define CACHE_ID_RELEASE_r0p0 0x00
41 #define CACHE_ID_RELEASE_r1p0 0x02
42 #define CACHE_ID_RELEASE_r2p0 0x04
43 #define CACHE_ID_RELEASE_r3p0 0x05
44 #define CACHE_ID_RELEASE_r3p1 0x06
45 #define CACHE_ID_RELEASE_r3p2 0x08
46 #define CACHE_ID_RELEASE_r3p3 0x09
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/src/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,sa8775p-mdss.yaml38 "^display-controller@[0-9a-f]+$":
46 "^displayport-controller@[0-9a-f]+$":
55 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
90 reg = <0x0ae00000 0x1000>;
111 iommus = <&apps_smmu 0x1000 0x402>;
119 reg = <0x0ae01000 0x8f000>,
120 <0x0aeb0000 0x2008>;
141 interrupts = <0>;
145 #size-cells = <0>;
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H A Dqcom,sm8750-mdss.yaml42 "^display-controller@[0-9a-f]+$":
49 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
88 reg = <0x0ae00000 0x1000>;
108 iommus = <&apps_smmu 0x800 0x2>;
119 reg = <0x0ae01000 0x93000>,
120 <0x0aeb0000 0x2008>;
124 interrupts-extended = <&mdss 0>;
146 #size-cells = <0>;
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/src/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_regs.h8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x820c0000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
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/src/sys/x86/cpufreq/
H A Dpowernow.c54 #define PN7_TYPE 0
58 #define A0_ERRATA 0x1 /* Bugs for the rev. A0 of Athlon (K7):
61 #define PENDING_STUCK 0x2 /* With some buggy chipset and some newer AMD64
67 #define PSB_START 0
68 #define PSB_STEP 0x10
71 #define PSB_OFF 0
93 #define MSR_AMDK7_FIDVID_CTL 0xc0010041
94 #define MSR_AMDK7_FIDVID_STATUS 0xc0010042
98 #define PN7_CTR_FID(x) ((x) & 0x1f)
99 #define PN7_CTR_VID(x) (((x) & 0x1f) << 8)
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/src/sys/x86/include/
H A Dspecialreg.h38 #define CR0_PE 0x00000001 /* Protected mode Enable */
39 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
40 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
41 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
42 #define CR0_PG 0x80000000 /* PaGing enable */
47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
48 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
50 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
51 #define CR0_NW 0x20000000 /* Not Write-through */
52 #define CR0_CD 0x40000000 /* Cache Disable */
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/src/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmmio.c25 [INT_SOURCE_CSR] = 0xd7010,
26 [INT_MASK_CSR] = 0xd7014,
27 [INT1_SOURCE_CSR] = 0xd7088,
28 [INT1_MASK_CSR] = 0xd708c,
29 [INT_MCU_CMD_SOURCE] = 0xd51f0,
30 [INT_MCU_CMD_EVENT] = 0x3108,
31 [WFDMA0_ADDR] = 0xd4000,
32 [WFDMA0_PCIE1_ADDR] = 0xd8000,
33 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
34 [CBTOP1_PHY_END] = 0x77ffffff,
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/src/lib/libpmc/pmu-events/arch/x86/westmereep-dp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/src/lib/libpmc/pmu-events/arch/x86/nehalemep/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/src/lib/libpmc/pmu-events/arch/x86/westmereex/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/src/lib/libpmc/pmu-events/arch/x86/nehalemex/
H A Dcache.json3 "EventCode": "0x63",
4 "Counter": "0,1",
5 "UMask": "0x2",
11 "EventCode": "0x63",
12 "Counter": "0,1",
13 "UMask": "0x1",
19 "EventCode": "0x51",
20 "Counter": "0,1",
21 "UMask": "0x4",
27 "EventCode": "0x51",
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/src/contrib/ofed/opensm/opensm/
H A Dosm_torus.c64 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
119 enum endpt_type { UNKNOWN = 0, SRCSINK, PASSTHRU };
189 * used as follows, assuming 0 <= d < N:
195 * traversing a link from link.end[0] to link.end[1] is always in the positive
267 * A torus dimension has coordinate values 0, 1, ..., radix - 1.
270 * radix - 1 and 0. The following specify the dateline location
273 * E.g. if the shared switch is at 0,0,0, the following are all
316 #define X_MESH (1U << 0)
347 for (s = 0; s < f->switch_cnt; s++) { in teardown_fabric()
352 for (p = 0; p < sw->port_cnt; p++) { in teardown_fabric()
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/src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dosprey_reg_map.h86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
88 volatile char pad__1[0x8]; /* 0xc - 0x14 */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
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/src/lib/libpmc/pmu-events/arch/x86/westmereep-sp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/src/sys/contrib/device-tree/src/arm64/qcom/
H A Dsa8775p.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
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H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
78 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0 0x100>;
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/src/sys/dev/mlx5/
H A Dmlx5_ifc.h32 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
33 MLX5_EVENT_TYPE_COMP = 0x0,
34 MLX5_EVENT_TYPE_PATH_MIG = 0x1,
35 MLX5_EVENT_TYPE_COMM_EST = 0x2,
36 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3,
37 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
38 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
39 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
40 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
41 MLX5_EVENT_TYPE_CQ_ERROR = 0x4,
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/src/share/misc/
H A Dusb_vendors33 0b21 AB13X Headset Adapter
308 0a01 ScanJet 2400c
309 0a17 color LaserJet 3700
310 0b01 ScanJet 82x0C
311 0b0c Wireless Keyboard and Optical Mouse receiver
312 0b17 LaserJet 2300d
313 0c17 LaserJet 1010
314 0c24 Bluetooth Dongle
315 0d12 OfficeJet 9100 series
316 0d17 LaserJet 1012
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/src/sys/dev/cxgbe/common/
H A Dt4_regs.h36 #define MYPF_BASE 0x1b000
39 #define PF0_BASE 0x1e000
42 #define PF1_BASE 0x1e400
45 #define PF2_BASE 0x1e800
48 #define PF3_BASE 0x1ec00
51 #define PF4_BASE 0x1f000
54 #define PF5_BASE 0x1f400
57 #define PF6_BASE 0x1f800
60 #define PF7_BASE 0x1fc00
63 #define PF_STRIDE 0x400
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