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/linux-6.15/drivers/pinctrl/mediatek/
Dpinctrl-mt8365.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
29 MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
30 MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
31 MTK_PIN_DRV_GRP(3, 0x710, 0, 2),
32 MTK_PIN_DRV_GRP(4, 0x710, 4, 2),
33 MTK_PIN_DRV_GRP(5, 0x710, 4, 2),
34 MTK_PIN_DRV_GRP(6, 0x710, 4, 2),
[all …]
/linux-6.15/drivers/gpu/drm/ci/xfails/
Di915-kbl-skips.txt47 # i915 0000:00:02.0: [drm] drm_WARN_ON((val & (1 << 30)) == 0)
48 # WARNING: CPU: 4 PID: 472 at drivers/gpu/drm/i915/display/intel_cdclk.c:944 skl_get_cdclk+0x1ca/0x…
50 # CPU: 4 UID: 0 PID: 472 Comm: device_reset Not tainted 6.13.0-rc2-ge95c88d68ac3 #1
52 # RIP: 0010:skl_get_cdclk+0x1ca/0x360
53 …0f 84 89 01 00 00 e8 e0 16 13 00 48 c7 c1 a0 71 5f 9a 4c 89 e2 48 c7 c7 67 56 69 9a 48 89 c6 e8 67…
67 # intel_update_cdclk+0x1c/0x90
68 # intel_cdclk_init_hw+0x46e/0x4c0
69 # intel_power_domains_init_hw+0x3eb/0x770
70 # intel_display_driver_probe_noirq+0x85/0x230
71 # i915_driver_probe+0x66d/0xc60
[all …]
/linux-6.15/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
Dhal_bt_coexist.h10 #define REG_HIGH_PRIORITY_TXRX 0x770
11 #define REG_LOW_PRIORITY_TXRX 0x774
25 #define BT_COEX_STATE_BT30 BIT(0)
60 #define BT_COEX_STATE_BT_CNT_LEVEL_0 BIT(0)
65 #define BT_RSSI_STATE_HIGH 0
72 #define BT_AGCTABLE_OFF 0
74 #define BT_BB_BACKOFF_OFF 0
76 #define BT_FW_NAV_OFF 0
79 #define BT_COEX_MECH_NONE 0
92 #define BT_DBG_PROFILE_NONE 0
[all …]
/linux-6.15/include/linux/usb/
Dusb338x.h19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
/linux-6.15/arch/arm/include/asm/hardware/
Dcache-l2x0.h15 #define L2X0_CACHE_ID 0x000
16 #define L2X0_CACHE_TYPE 0x004
17 #define L2X0_CTRL 0x100
18 #define L2X0_AUX_CTRL 0x104
19 #define L310_TAG_LATENCY_CTRL 0x108
20 #define L310_DATA_LATENCY_CTRL 0x10C
21 #define L2X0_EVENT_CNT_CTRL 0x200
22 #define L2X0_EVENT_CNT1_CFG 0x204
23 #define L2X0_EVENT_CNT0_CFG 0x208
24 #define L2X0_EVENT_CNT1_VAL 0x20C
[all …]
/linux-6.15/arch/arm/boot/dts/nxp/imx/
Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/linux-6.15/Documentation/devicetree/bindings/display/msm/
Dqcom,sa8775p-mdss.yaml38 "^display-controller@[0-9a-f]+$":
46 "^displayport-controller@[0-9a-f]+$":
55 "^phy@[0-9a-f]+$":
79 reg = <0x0ae00000 0x1000>;
100 iommus = <&apps_smmu 0x1000 0x402>;
108 reg = <0x0ae01000 0x8f000>,
109 <0x0aeb0000 0x2008>;
130 interrupts = <0>;
134 #size-cells = <0>;
136 port@0 {
[all …]
/linux-6.15/drivers/gpu/drm/radeon/
Dtrinityd.h30 #define CG_CGTT_LOCAL_0 0x0
31 #define CG_CGTT_LOCAL_1 0x1
34 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000
35 # define STATE_VALID(x) ((x) << 0)
36 # define STATE_VALID_MASK (0xff << 0)
37 # define STATE_VALID_SHIFT 0
39 # define CLK_DIVIDER_MASK (0xff << 8)
42 # define VID_MASK (0xff << 16)
45 # define LVRT_MASK (0xff << 24)
47 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004
[all …]
Dsumod.h30 #define RCU_FW_VERSION 0x30c
32 #define RCU_PWR_GATING_SEQ0 0x408
33 #define RCU_PWR_GATING_SEQ1 0x40c
34 #define RCU_PWR_GATING_CNTL 0x410
35 # define PWR_GATING_EN (1 << 0)
36 # define RSVD_MASK (0x3 << 1)
38 # define PCV_MASK (0x1f << 3)
41 # define PCP_MASK (0xf << 8)
44 # define RPW_MASK (0xf << 16)
47 # define ID_MASK (0xf << 24)
[all …]
/linux-6.15/drivers/net/ethernet/apple/
Dbmac.h17 #define XIFC 0x000 /* low-level interface control */
18 # define TxOutputEnable 0x0001 /* output driver enable */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
21 # define MIILoopbackBits 0x0006
22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
23 # define SQETestEnable 0x0010 /* SQE test enable */
24 # define SQETimeWindow 0x03e0 /* SQE time window */
25 # define XIFLanceMode 0x0010 /* Lance mode enable */
26 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
[all …]
/linux-6.15/include/linux/mfd/mt6331/
Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
[all …]
/linux-6.15/drivers/clk/stm32/
Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
/linux-6.15/drivers/net/wireless/mediatek/mt76/
Dmt792x_regs.h8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x820c0000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
[all …]
/linux-6.15/drivers/memory/tegra/
Dtegra210-emc.h21 #define EMC_INTSTATUS 0x0
23 #define EMC_DBG 0x8
26 #define EMC_CFG 0xc
31 #define EMC_PIN 0x24
32 #define EMC_PIN_PIN_CKE BIT(0)
35 #define EMC_TIMING_CONTROL 0x28
36 #define EMC_RC 0x2c
37 #define EMC_RFC 0x30
38 #define EMC_RAS 0x34
39 #define EMC_RP 0x38
[all …]
Dtegra194.c19 .override = 0x000,
20 .security = 0x004,
29 .override = 0x008,
30 .security = 0x00c,
39 .override = 0x010,
40 .security = 0x014,
49 .override = 0x0a8,
50 .security = 0x0ac,
59 .override = 0x0b0,
60 .security = 0x0b4,
[all …]
/linux-6.15/arch/arm/mach-imx/
Dpm-imx6.c31 #define CCR 0x0
32 #define BM_CCR_WB_COUNT (0x7 << 16)
33 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
34 #define BM_CCR_RBC_EN (0x1 << 27)
36 #define CLPCR 0x54
37 #define BP_CLPCR_LPM 0
38 #define BM_CLPCR_LPM (0x3 << 0)
39 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
40 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
41 #define BM_CLPCR_SBYOS (0x1 << 6)
[all …]
/linux-6.15/drivers/net/wireless/ath/carl9170/
Dhw.h43 #define AR9170_UART_REG_BASE 0x1c0000
46 #define AR9170_UART_REG_RX_BUFFER (AR9170_UART_REG_BASE + 0x000)
47 #define AR9170_UART_REG_TX_HOLDING (AR9170_UART_REG_BASE + 0x004)
48 #define AR9170_UART_REG_FIFO_CONTROL (AR9170_UART_REG_BASE + 0x010)
49 #define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO 0x02
50 #define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO 0x04
52 #define AR9170_UART_REG_LINE_CONTROL (AR9170_UART_REG_BASE + 0x014)
53 #define AR9170_UART_REG_MODEM_CONTROL (AR9170_UART_REG_BASE + 0x018)
54 #define AR9170_UART_MODEM_CTRL_DTR_BIT 0x01
55 #define AR9170_UART_MODEM_CTRL_RTS_BIT 0x02
[all …]
/linux-6.15/drivers/media/platform/qcom/camss/
Dcamss-vfe-4-1.c19 #define VFE_0_HW_VERSION 0x000
21 #define VFE_0_GLOBAL_RESET_CMD 0x00c
22 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0)
32 #define VFE_0_MODULE_CFG 0x018
38 #define VFE_0_CORE_CFG 0x01c
39 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4
40 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5
41 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6
42 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7
44 #define VFE_0_IRQ_CMD 0x024
[all …]
/linux-6.15/drivers/net/ethernet/mediatek/
Dmtk_wed.c24 #define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
38 #define MTK_WED_MAX_GROUP_SIZE 0x100
39 #define MTK_WED_VLD_GROUP_SIZE 0x40
61 .tx_bm_tkid = 0x088,
62 .wpdma_rx_ring0 = 0x770,
63 .reset_idx_tx_mask = GENMASK(3, 0),
72 .tx_bm_tkid = 0x0c8,
73 .wpdma_rx_ring0 = 0x770,
74 .reset_idx_tx_mask = GENMASK(1, 0),
83 .tx_bm_tkid = 0x0c8,
[all …]
/linux-6.15/drivers/net/wireless/mediatek/mt76/mt7915/
Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/linux-6.15/drivers/comedi/drivers/
Dni_660x.c81 #define NI660X_DMA_CFG_SEL(_c, _s) (((_s) & 0x1f) << (8 * (_c)))
82 #define NI660X_DMA_CFG_SEL_MASK(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
83 #define NI660X_DMA_CFG_SEL_NONE(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
84 #define NI660X_DMA_CFG_RESET(_c) NI660X_DMA_CFG_SEL((_c), 0x80)
87 #define NI660X_IO_CFG_OUT_SEL(_c, _s) (((_s) & 0x3) << (((_c) % 2) ? 0 : 8))
88 #define NI660X_IO_CFG_OUT_SEL_MASK(_c) NI660X_IO_CFG_OUT_SEL((_c), 0x3)
89 #define NI660X_IO_CFG_IN_SEL(_c, _s) (((_s) & 0x7) << (((_c) % 2) ? 4 : 12))
90 #define NI660X_IO_CFG_IN_SEL_MASK(_c) NI660X_IO_CFG_IN_SEL((_c), 0x7)
98 [NITIO_G0_INT_ACK] = { 0x004, 2 }, /* write */
99 [NITIO_G0_STATUS] = { 0x004, 2 }, /* read */
[all …]
/linux-6.15/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbtc8821a1ant.c35 static u32 glcoex_ver_8821a_1ant = 0x41;
47 long bt_rssi = 0; in btc8821a1ant_bt_rssi_state()
135 long wifi_rssi = 0; in btc8821a1ant_wifi_rssi_state()
245 case 0: /* normal mode */ in btc8821a1ant_auto_rate_fb_retry()
246 btcoexist->btc_write_4byte(btcoexist, 0x430, in btc8821a1ant_auto_rate_fb_retry()
248 btcoexist->btc_write_4byte(btcoexist, 0x434, in btc8821a1ant_auto_rate_fb_retry()
256 btcoexist->btc_write_4byte(btcoexist, 0x430, in btc8821a1ant_auto_rate_fb_retry()
257 0x0); in btc8821a1ant_auto_rate_fb_retry()
258 btcoexist->btc_write_4byte(btcoexist, 0x434, in btc8821a1ant_auto_rate_fb_retry()
259 0x01010101); in btc8821a1ant_auto_rate_fb_retry()
[all …]

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