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/linux-6.8/drivers/clk/qcom/
Dgcc-sm8450.c40 .offset = 0x0,
43 .enable_reg = 0x62018,
44 .enable_mask = BIT(0),
57 { 0x1, 2 },
62 .offset = 0x0,
79 .offset = 0x4000,
82 .enable_reg = 0x62018,
96 .offset = 0x9000,
99 .enable_reg = 0x62018,
113 { P_BI_TCXO, 0 },
[all …]
Dgcc-qdu1000.c51 .offset = 0x0,
54 .enable_reg = 0x62018,
55 .enable_mask = BIT(0),
68 { 0x1, 2 }
72 .offset = 0x0,
89 .offset = 0x1000,
92 .enable_reg = 0x62018,
106 .offset = 0x1000,
123 .offset = 0x2000,
126 .enable_reg = 0x62018,
[all …]
Dgcc-sm4450.c52 { 249600000, 2020000000, 0 },
56 .offset = 0x0,
59 .enable_reg = 0x62018,
60 .enable_mask = BIT(0),
73 { 0x1, 2 },
78 .offset = 0x0,
95 { 0x2, 3 },
100 .offset = 0x0,
117 .offset = 0x1000,
120 .enable_reg = 0x62018,
[all …]
Dgcc-sa8775p.c76 .offset = 0x0,
79 .enable_reg = 0x4b028,
80 .enable_mask = BIT(0),
91 { 0x1, 2 },
96 .offset = 0x0,
113 .offset = 0x1000,
116 .enable_reg = 0x4b028,
128 .offset = 0x4000,
131 .enable_reg = 0x4b028,
143 .offset = 0x5000,
[all …]
Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
/linux-6.8/Documentation/devicetree/bindings/interconnect/
Dqcom,rpm.yaml45 reg = <0x00400000 0x62000>;
Dqcom,msm8939.yaml61 reg = <0x00580000 0x14000>;
67 reg = <0x00400000 0x62000>;
/linux-6.8/arch/arm/mach-omap2/
Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
Domap34xx.h17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
/linux-6.8/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm6858.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
39 reg = <0x0 0x2>;
47 reg = <0x0 0x3>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0x0 0x0 0x81000000 0x8000>;
105 reg = <0x1000 0x1000>, /* GICD */
[all …]
/linux-6.8/drivers/gpu/drm/i915/display/
Dintel_audio_regs.h11 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
16 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
18 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
19 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
22 #define _IBX_AUD_CNTL_ST_A 0xE20B4
23 #define _IBX_AUD_CNTL_ST_B 0xE21B4
29 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
31 #define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
33 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
34 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
[all …]
Dintel_display_device.c22 #define PIPE_A_OFFSET 0x70000
23 #define PIPE_B_OFFSET 0x71000
24 #define PIPE_C_OFFSET 0x72000
25 #define PIPE_D_OFFSET 0x73000
26 #define CHV_PIPE_C_OFFSET 0x74000
33 #define PIPE_EDP_OFFSET 0x7f000
35 /* ICL DSI 0 and 1 */
36 #define PIPE_DSI0_OFFSET 0x7b000
37 #define PIPE_DSI1_OFFSET 0x7b800
39 #define TRANSCODER_A_OFFSET 0x60000
[all …]
/linux-6.8/arch/arm/boot/dts/ti/omap/
Dam4372.dtsi20 memory@0 {
22 reg = <0 0>;
42 #size-cells = <0>;
43 cpu: cpu@0 {
47 reg = <0>;
77 opp-supported-hw = <0xFF 0x01>;
85 opp-supported-hw = <0xFF 0x04>;
92 opp-supported-hw = <0xFF 0x08>;
99 opp-supported-hw = <0xFF 0x10>;
106 opp-supported-hw = <0xFF 0x20>;
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/linux-6.8/drivers/interconnect/qcom/
Dmsm8916.c154 .qos.areq_prio = 0,
155 .qos.prio_level = 0,
156 .qos.qos_port = 0,
217 .qos.areq_prio = 0,
218 .qos.prio_level = 0,
237 .qos.areq_prio = 0,
238 .qos.prio_level = 0,
257 .qos.areq_prio = 0,
258 .qos.prio_level = 0,
441 .qos.areq_prio = 0,
[all …]
Dmsm8939.c157 .qos.areq_prio = 0,
158 .qos.prio_level = 0,
159 .qos.qos_port = 0,
220 .qos.areq_prio = 0,
221 .qos.prio_level = 0,
240 .qos.areq_prio = 0,
241 .qos.prio_level = 0,
260 .qos.areq_prio = 0,
261 .qos.prio_level = 0,
280 .qos.areq_prio = 0,
[all …]
/linux-6.8/drivers/gpu/drm/gma500/
Dpsb_intel_reg.h11 #define GPIOA 0x5010
12 #define GPIOB 0x5014
13 #define GPIOC 0x5018
14 #define GPIOD 0x501c
15 #define GPIOE 0x5020
16 #define GPIOF 0x5024
17 #define GPIOG 0x5028
18 #define GPIOH 0x502c
19 # define GPIO_CLOCK_DIR_MASK (1 << 0)
20 # define GPIO_CLOCK_DIR_IN (0 << 1)
[all …]
/linux-6.8/arch/arm64/boot/dts/qcom/
Dmsm8939.dtsi30 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #size-cells = <0>;
49 reg = <0x100>;
67 reg = <0x101>;
80 reg = <0x102>;
93 reg = <0x103>;
102 CPU4: cpu@0 {
106 reg = <0x0>;
124 reg = <0x1>;
[all …]
Dmsm8916.dtsi27 reg = <0 0x80000000 0 0>;
36 reg = <0x0 0x86000000 0x0 0x300000>;
42 reg = <0x0 0x86300000 0x0 0x100000>;
50 reg = <0x0 0x86400000 0x0 0x100000>;
55 reg = <0x0 0x86500000 0x0 0x180000>;
60 reg = <0x0 0x86680000 0x0 0x80000>;
66 reg = <0x0 0x86700000 0x0 0xe0000>;
73 reg = <0x0 0x867e0000 0x0 0x20000>;
85 * alignment = <0x0 0x400000>;
86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
[all …]
/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_1_8_0_offset.h29 // base address: 0x60000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]