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Searched +full:0 +full:x5c000 (Results 1 – 17 of 17) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3576-cru.yaml53 reg = <0xfd7c0000 0x5c000>;
/linux/drivers/gpu/drm/amd/include/asic_reg/clk/
H A Dclk_11_5_0_offset.h26 // base address: 0x5c000
27 #define mmCLK1_0_CLK1_CLK_PLL_REQ 0x0410
28 #define mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX 0
29 #define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL 0x044a
30 #define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX 0
31 #define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL 0x0454
32 #define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX 0
33 #define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL 0x045e
34 #define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX 0
[all...]
/linux/arch/powerpc/boot/dts/fsl/
H A Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x100
[all...]
/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,comphy-cp110.yaml32 - description: Lane 0 (USB3/GbE) registers (Armada 3700)
47 const: 0
64 '^phy@[0-2]$':
108 reg = <0x120000 0x6000>;
112 #size-cells = <0>;
115 phy@0 {
116 reg = <0>;
129 reg = <0x18300 0x30
[all...]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-37xx.dtsi33 reg = <0 0x4000000 0 0x200000>;
38 reg = <0 0x4400000 0 0x1000000>;
45 #size-cells = <0>;
46 cpu0: cpu@0 {
[all...]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-s4.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0 0x0>;
30 reg = <0x0 0x1>;
37 reg = <0x0 0x2>;
44 reg = <0x0 0x
[all...]
H A Damlogic-c3.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
53 #clock-cells = <0>;
67 reg = <0x0 0x07f50e00 0x
[all...]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x20
[all...]
/linux/drivers/scsi/qla2xxx/
H A Dqla_fw.h14 #define MBS_CHECKSUM_ERROR 0x4010
15 #define MBS_INVALID_PRODUCT_KEY 0x4020
55 #define PDS_PLOGI_PENDING 0x03
56 #define PDS_PLOGI_COMPLETE 0x04
57 #define PDS_PRLI_PENDING 0x05
58 #define PDS_PRLI_COMPLETE 0x06
59 #define PDS_PORT_UNAVAILABLE 0x07
60 #define PDS_PRLO_PENDING 0x09
61 #define PDS_LOGO_PENDING 0x11
62 #define PDS_PRLI2_PENDING 0x1
[all...]
/linux/drivers/clk/qcom/
H A Dgcc-msm8917.c54 .offset = 0x21000,
57 .enable_reg = 0x45008,
72 .offset = 0x21000,
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
89 .offset = 0x21000,
102 { 700000000, 1400000000, 0 },
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
114 .offset = 0x2200
[all...]
H A Dgcc-qcs8300.c60 .offset = 0x0,
63 .enable_reg = 0x4b028,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
99 .offset = 0x1000,
102 .enable_reg = 0x4b028,
116 .offset = 0x4000,
119 .enable_reg = 0x4b028,
133 .offset = 0x700
[all...]
H A Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x100
[all...]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a00
[all...]
H A Dgcc-msm8953.c40 .offset = 0x21000,
43 .enable_reg = 0x45000,
44 .enable_mask = BIT(0),
70 .offset = 0x21000,
83 .offset = 0x4a000,
86 .enable_reg = 0x45000,
100 .offset = 0x4a000,
113 { 1000000000, 2000000000, 0 },
118 .config_ctl_val = 0x4001055b,
119 .early_output_mask = 0,
[all...]
H A Dgcc-sa8775p.c74 .offset = 0x0,
77 .enable_reg = 0x4b028,
78 .enable_mask = BIT(0),
89 { 0x1, 2 },
94 .offset = 0x0,
111 .offset = 0x1000,
114 .enable_reg = 0x4b028,
126 .offset = 0x4000,
129 .enable_reg = 0x4b028,
141 .offset = 0x500
[all...]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192f.c18 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
19 {0x430, 0x0
[all...]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-base.dtsi57 #size-cells = <0>;
92 cpu_l0: cpu@0 {
95 reg = <0x0>;
114 reg = <0x100>;
133 reg = <0x200>;
152 reg = <0x300>;
171 reg = <0x400>;
190 reg = <0x500>;
209 reg = <0x600>;
228 reg = <0x70
[all...]