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/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/linux-5.10/arch/arm/boot/dts/
Dexynos54xx.dtsi42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
78 reg = <0x101c0000 0xb00>;
95 reg = <0x101d0000 0x100>;
101 reg = <0x12d10000 0x100>;
111 reg = <0x12ca0000 0x1000>;
[all …]
Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
[all …]
/linux-5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml143 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
147 ranges = <0 0x5c000000 0x40000>;
150 reg = <0x100 0x50>;
154 reg = <0x1000 0x1000>;
159 reg = <0x20000 0x20000>;
174 reg = <0x02020000 0x54000>;
177 ranges = <0 0x02020000 0x54000>;
179 smp-sram@0 {
181 reg = <0x0 0x1000>;
186 reg = <0x53000 0x1000>;
[all …]
/linux-5.10/arch/powerpc/boot/dts/fsl/
Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x0/
Dpci_mcu.c11 #define MT_MCU_IVB_ADDR (MT_MCU_ILM_ADDR + 0x54000 - MT_MCU_IVB_SIZE)
15 bool is_combo_chip = mt76_chip(&dev->mt76) != 0x7610; in mt76x0e_load_firmware()
16 u32 val, ilm_len, dlm_len, offset = 0; in mt76x0e_load_firmware()
52 (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf); in mt76x0e_load_firmware()
57 (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf, in mt76x0e_load_firmware()
68 mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0); in mt76x0e_load_firmware()
93 mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0); in mt76x0e_load_firmware()
95 mt76_wr(dev, MT_MCU_INT_LEVEL, 0x3); in mt76x0e_load_firmware()
97 mt76_wr(dev, MT_MCU_RESET_CTL, 0x300); in mt76x0e_load_firmware()
110 mt76_wr(dev, MT_MCU_SEMAPHORE_00, 0x1); in mt76x0e_load_firmware()
[all …]
/linux-5.10/drivers/infiniband/hw/qib/
Dqib_6120_regs.h35 #define QIB_6120_Revision_OFFS 0x0
36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
38 #define QIB_6120_Revision_Reserved_LSB 0x28
39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
40 #define QIB_6120_Revision_BoardID_LSB 0x20
41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
42 #define QIB_6120_Revision_R_SW_LSB 0x18
43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
44 #define QIB_6120_Revision_R_Arch_LSB 0x10
[all …]
/linux-5.10/drivers/staging/rtl8712/
Drtl871x_mp.c26 pmp_priv->curr_rateidx = 0; in _init_mp_priv_()
27 pmp_priv->curr_txpoweridx = 0x14; in _init_mp_priv_()
30 pmp_priv->check_mp_pkt = 0; in _init_mp_priv_()
31 pmp_priv->tx_pktcount = 0; in _init_mp_priv_()
32 pmp_priv->rx_pktcount = 0; in _init_mp_priv_()
33 pmp_priv->rx_crcerrpktcount = 0; in _init_mp_priv_()
54 for (i = 0; i < NR_MP_XMITFRAME; i++) { in init_mp_priv()
64 return 0; in init_mp_priv()
70 return 0; in free_mp_priv()
93 u32 cmd32 = 0, val32 = 0; in fw_iocmd_read()
[all …]
/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.c46 #define INTF_SDM845_MASK (0)
69 .max_mixer_blendstages = 0xb,
85 .max_mixer_blendstages = 0x9,
97 .max_mixer_blendstages = 0xb,
113 .max_mixer_blendstages = 0xb,
129 .base = 0x0, .len = 0x45C,
130 .features = 0,
131 .highest_bank_bit = 0x2,
133 .reg_off = 0x2AC, .bit_off = 0},
135 .reg_off = 0x2B4, .bit_off = 0},
[all …]
/linux-5.10/drivers/scsi/qla2xxx/
Dqla_fw.h14 #define MBS_CHECKSUM_ERROR 0x4010
15 #define MBS_INVALID_PRODUCT_KEY 0x4020
55 #define PDS_PLOGI_PENDING 0x03
56 #define PDS_PLOGI_COMPLETE 0x04
57 #define PDS_PRLI_PENDING 0x05
58 #define PDS_PRLI_COMPLETE 0x06
59 #define PDS_PORT_UNAVAILABLE 0x07
60 #define PDS_PRLO_PENDING 0x09
61 #define PDS_LOGO_PENDING 0x11
62 #define PDS_PRLI2_PENDING 0x12
[all …]
/linux-5.10/drivers/clk/qcom/
Dgcc-msm8916.c46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
[all …]
Dgcc-msm8939.c54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
/linux-5.10/drivers/media/pci/saa7134/
Dsaa7134-cards.c48 .fm_radio = { .if_freq = 5500, .fm_rfn = 0, .agc_mode = 3, .std = 0,
49 .if_lvl = 0, .rfagc_top = 0x2c, },
58 .audio_clock = 0x00187de7,
66 .vmux = 0,
73 .audio_clock = 0x00187de7,
81 .vmux = 0,
100 .audio_clock = 0x00200000,
106 .gpiomask = 0xe000,
111 .gpio = 0x8000,
116 .gpio = 0x0000,
[all …]
/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]