Searched +full:0 +full:x50000000 (Results 1 – 25 of 214) sorted by relevance
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| /linux-5.10/arch/arm/boot/dts/ |
| D | spear300.dtsi | 15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
49 shirq: interrupt-controller@0x50000000 {
[all …]
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| D | spear13xx.dtsi | 15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04
43 0 7 0x04>;
48 reg = <0xed000000 0x1000>;
56 reg = <0 0x40000000>;
79 ranges = <0x50000000 0x50000000 0x10000000
[all …]
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| D | intel-ixp43x-gateworks-gw2358.dts | 16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
66 reg = <0x56>;
73 reg = <0x57>;
83 * 32 MB of Flash in 0x20000 byte blocks
[all …]
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| D | intel-ixp42x-linksys-nslu2.dts | 17 memory@0 {
20 reg = <0x00000000 0x2000000>;
36 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
79 #size-cells = <0>;
83 reg = <0x6f>;
98 * 8 MB of Flash in 0x20000 byte blocks
99 * mapped in at 0x50000000
101 reg = <0x50000000 0x800000>;
105 /* Eraseblock at 0x7e0000 */
106 fis-index-block = <0x3f>;
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| D | versatile-pb.dts | 11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
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| D | zx296702-ad1.dts | 18 reg = <0x50000000 0x20000000>;
28 slot@0 {
29 reg = <0>;
40 slot@0 {
41 reg = <0>;
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| D | gemini.dtsi | 23 pinctrl-0 = <&pflash_default_pins>;
33 reg = <0x40000000 0x1000>;
41 offset = <0x0c>;
43 mask = <0xC0000000>;
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
161 reg = <0x41000000 0x1000>;
170 reg = <0x42000000 0x100>;
175 pinctrl-0 = <&uart_default_pins>;
181 reg = <0x43000000 0x1000>;
195 reg = <0x45000000 0x100>;
[all …]
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| /linux-5.10/arch/arm/mach-imx/ |
| D | hardware.h | 21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
41 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
43 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
44 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
45 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
47 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
48 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
51 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
[all …]
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| D | mx31.h | 5 #define MX31_AIPS1_BASE_ADDR 0x43f00000
7 #define MX31_SPBA0_BASE_ADDR 0x50000000
9 #define MX31_AIPS2_BASE_ADDR 0x53f00000
11 #define MX31_AVIC_BASE_ADDR 0x68000000
13 #define MX31_X_MEMC_BASE_ADDR 0xb8000000
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| D | mx35.h | 5 #define MX35_AIPS1_BASE_ADDR 0x43f00000
7 #define MX35_SPBA0_BASE_ADDR 0x50000000
9 #define MX35_AIPS2_BASE_ADDR 0x53f00000
11 #define MX35_AVIC_BASE_ADDR 0x68000000
13 #define MX35_X_MEMC_BASE_ADDR 0xb8000000
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| /linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am65.dtsi | 68 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
69 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
70 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
71 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
72 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
73 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
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| D | k3-j7200.dtsi | 39 #size-cells = <0>;
53 cpu0: cpu@0 {
55 reg = <0x000>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
69 reg = <0x001>;
72 i-cache-size = <0xc000>;
75 d-cache-size = <0x8000>;
85 cache-size = <0x100000>;
125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
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| D | k3-j721e.dtsi | 40 #size-cells = <0>;
54 cpu0: cpu@0 {
56 reg = <0x000>;
59 i-cache-size = <0xC000>;
62 d-cache-size = <0x8000>;
70 reg = <0x001>;
73 i-cache-size = <0xC000>;
76 d-cache-size = <0x8000>;
86 cache-size = <0x100000>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | mailbox.txt | 36 mboxes = <&mailbox 0 &mailbox 1>;
43 reg = <0x50000000 0x10000>;
47 ranges = <0 0x50000000 0x10000>;
49 cl_shmem: shmem@0 {
51 reg = <0x0 0x200>;
57 mboxes = <&mailbox 0>;
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| /linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | versatile.yaml | 38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
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| D | faraday,ftpci100.txt | 9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
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| D | v3-v360epc-pci.txt | 18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
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| D | tango-pcie.txt | 19 reg = <0x50000000 0x400000>, <0x2e000 0x100>;
20 bus-range = <0 3>;
25 ranges = <0x02000000 0x0 0x00400000 0x50400000 0x0 0x3c00000>;
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| /linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phytbl_lcn.c | 10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | atmel-at91_cf.txt | 8 optional and may be set to 0 if not present.
13 reg = <0x50000000 0x30000000>;
14 gpios = <&pioC 13 0 /* irq */
15 &pioC 15 0 /* detect */
16 0 /* vcc */
17 &pioC 5 0 /* reset */
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| /linux-5.10/arch/m68k/include/asm/ |
| D | sun3x.h | 6 #define SUN3X_IOMMU 0x60000000
7 #define SUN3X_ENAREG 0x61000000
8 #define SUN3X_INTREG 0x61001400
9 #define SUN3X_DIAGREG 0x61001800
10 #define SUN3X_ZS1 0x62000000
11 #define SUN3X_ZS2 0x62002000
12 #define SUN3X_LANCE 0x65002000
13 #define SUN3X_EEPROM 0x64000000
14 #define SUN3X_IDPROM 0x640007d8
15 #define SUN3X_VIDEO_BASE 0x50000000
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | intel,ixp4xx-flash.txt | 20 reg = <0x50000000 0x01000000>;
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| /linux-5.10/arch/powerpc/boot/dts/ |
| D | klondike.dts | 16 dcr-parent = <&{/cpus/cpu@0}>;
25 #size-cells = <0>;
27 cpu@0 {
30 reg = <0x00000000>;
44 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
50 cell-index = <0>;
51 dcr-reg = <0x0c0 0x010>;
52 #address-cells = <0>;
53 #size-cells = <0>;
61 dcr-reg = <0x0d0 0x010>;
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/media/ |
| D | pxa-camera.txt | 19 reg = <0x50000000 0x1000>;
30 #size-cells = <0>;
33 qci: endpoint@0 {
34 reg = <0>; /* Local endpoint # */
37 hsync-active = <0>; /* Active low */
38 vsync-active = <0>; /* Active low */
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| /linux-5.10/arch/arm/mach-omap2/ |
| D | omap44xx.h | 17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
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