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Searched +full:0 +full:x48600000 (Results 1 – 8 of 8) sorted by relevance

/src/sys/contrib/device-tree/Bindings/dma/ti/
H A Dk3-bcdma.yaml51 0 - split channel
57 if cell 1 is 0 (split channel):
60 for source thread IDs (rx): 0 - 0x7fff
61 for destination thread IDs (tx): 0x8000 - 0xffff
96 maximum: 0x3f
107 maximum: 0x3f
118 maximum: 0x3f
244 reg = <0x0 0x485c0100 0x0 0x100>,
245 <0x0 0x4c000000 0x0 0x20000>,
246 <0x0 0x4a820000 0x0 0x20000>,
[all …]
/src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62a-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x01 0x00000000 0x00 0x2000>, /* GICC */
22 <0x01 0x00010000 0x00 0x1000>, /* GICH */
23 <0x01 0x00020000 0x00 0x2000>; /* GICV */
37 reg = <0x00 0x01820000 0x00 0x10000>;
38 socionext,synquacer-pre-its = <0x1000000 0x400000>;
48 ranges = <0x00 0x00 0x00100000 0x20000>;
[all …]
H A Dk3-am62p-j722s-common-main.dtsi22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
24 <0x01 0x00000000 0x00 0x2000>, /* GICC */
25 <0x01 0x00010000 0x00 0x1000>, /* GICH */
26 <0x01 0x00020000 0x00 0x2000>; /* GICV */
35 reg = <0x00 0x01820000 0x00 0x10000>;
36 socionext,synquacer-pre-its = <0x1000000 0x400000>;
44 reg = <0x00 0x00100000 0x00 0x20000>;
47 ranges = <0x00 0x00 0x00100000 0x20000>;
51 reg = <0x4044 0x8>;
[all …]
H A Dk3-am62-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x01 0x00000000 0x00 0x2000>, /* GICC */
27 <0x01 0x00010000 0x00 0x1000>, /* GICH */
28 <0x01 0x00020000 0x00 0x2000>; /* GICV */
37 reg = <0x00 0x01820000 0x00 0x10000>;
38 socionext,synquacer-pre-its = <0x1000000 0x400000>;
48 ranges = <0x0 0x00 0x00100000 0x20000>;
[all …]
H A Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMask.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 0xf0000000,
18 0xb0000000,
19 0x0fe03fe0,
20 0 },
23 0xffc00000,
24 0x76000000,
25 0x00203fe0,
26 0 },
29 0xff800000,
[all …]
/src/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
/src/sys/dev/bxe/
H A D57710_init_values.c55 {OP_WR, 0x600dc, 0x1},
56 {OP_SW, 0x61000, 0x2000000},
57 {OP_RD, 0x600d8, 0x0},
58 {OP_SW, 0x60200, 0x30200},
59 {OP_WR, 0x600dc, 0x0},
62 {OP_WR, 0x60068, 0xb8},
63 {OP_WR, 0x60078, 0x114},
64 {OP_RD, 0x600b8, 0x0},
65 {OP_RD, 0x600c8, 0x0},
68 {OP_WR, 0x6006c, 0xb8},
[all …]