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/src/sys/contrib/device-tree/Bindings/sound/
H A Ddavinci-mcasp-audio.yaml35 description: 0 - I2S or 1 - DIT operation mode
37 - 0
52 0 - Inactive, 1 - TX, 2 - RX
58 minimum: 0
83 0 disables the FIFO use
90 0 disables the FIFO use
97 0 - 3-state, 2 - logic low, 3 - logic high
99 - 0
154 const: 0
175 - 0
[all …]
/src/sys/libkern/
H A Dcrc16.c32 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */
34 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
35 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
36 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
37 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
38 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
39 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
40 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
41 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
42 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/src/tools/diag/dumpvfscache/
H A Ddumpvfscache.c16 0x0000, 0xCC01, 0xD801, 0x1400,
17 0xF001, 0x3C00, 0x2800, 0xE401,
18 0xA001, 0x6C00, 0x7800, 0xB401,
19 0x5000, 0x9C01, 0x8801, 0x4400
31 char nc_name[0];
37 u_short crc = 0; in wlpsacrc()
40 for (i = 0; i < len; i++, buf++) { in wlpsacrc()
42 r1 = crc16_table[crc & 0xF]; in wlpsacrc()
43 crc = (crc >> 4) & 0x0FFF; in wlpsacrc()
44 crc = crc ^ r1 ^ crc16_table[*buf & 0xF]; in wlpsacrc()
[all …]
/src/sys/dev/gpio/
H A Dchvgpio_reg.h47 #define CHVGPIO_INTERRUPT_STATUS 0x0300
48 #define CHVGPIO_INTERRUPT_MASK 0x0380
49 #define CHVGPIO_PAD_CFG0 0x4400
50 #define CHVGPIO_PAD_CFG1 0x4404
52 #define CHVGPIO_PAD_CFG0_GPIORXSTATE 0x00000001
53 #define CHVGPIO_PAD_CFG0_GPIOTXSTATE 0x00000002
54 #define CHVGPIO_PAD_CFG0_INTSEL_MASK 0xf0000000
59 #define CHVGPIO_PAD_CFG0_GPIOCFG_GPIO 0
64 #define CHVGPIO_PAD_CFG1_INTWAKECFG_MASK 0x00000007
65 #define CHVGPIO_PAD_CFG1_INTWAKECFG_FALLING 0x00000001
[all …]
/src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-mcu.dtsi13 ranges = <0x0 0x0 0x40f00000 0x20000>;
17 reg = <0x200 0x8>;
22 reg = <0x4040 0x4>;
30 reg = <0x0 0x40f04200 0x0 0x10>;
33 pinctrl-single,function-mask = <0x00000101>;
39 reg = <0x0 0x40f04280 0x0 0x8>;
42 pinctrl-single,function-mask = <0x00000003>;
47 reg = <0x00 0x40a00000 0x00 0x100>;
56 reg = <0x00 0x41c00000 0x00 0x80000>;
57 ranges = <0x0 0x00 0x41c00000 0x80000>;
[all …]
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
H A Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
/src/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm63138.dtsi23 #size-cells = <0>;
25 cpu@0 {
29 reg = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
80 ranges = <0 0x80000000 0x784000>;
86 reg = <0x1d000 0x1000>;
92 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/src/sys/contrib/device-tree/src/arm/microchip/
H A Dsama7d65.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
31 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32 KB
36 i-cache-size = <0x8000>; // L1, 32 KB
42 cache-size = <0x40000>; // L2, 256 KB
52 #clock-cells = <0>;
58 #clock-cells = <0>;
64 reg = <0x100000 0x20000>;
78 reg = <0xe0000800 0x4000>;
[all …]
H A Dsama7g5.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
41 d-cache-size = <0x8000>; // L1, 32 KB
42 i-cache-size = <0x8000>; // L1, 32 KB
48 cache-size = <0x40000>; // L2, 256 KB
98 hysteresis = <0>;
104 hysteresis = <0>;
110 hysteresis = <0>;
133 #clock-cells = <0>;
[all …]
/src/share/i18n/csmapper/CNS/
H A DCNS11643-5%UCS@BMP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
13 # Unicode version: 5.0.0
47 0x2141 = 0x355A
48 0x2174 = 0x3CBC
49 0x217D = 0x49B9
50 0x2230 = 0x34DE
51 0x223C = 0x3543
52 0x2250 = 0x37AC
53 0x2251 = 0x37AA
[all …]
H A DUCS@BMP%CNS11643-5.src5 SRC_ZONE 0x3441 - 0x9E77
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.0.0
47 0x3441 = 0x2334
48 0x344A = 0x2525
49 0x344E = 0x252B
50 0x345B = 0x2821
51 0x3463 = 0x2B6C
52 0x3482 = 0x4457
53 0x349B = 0x5359
[all …]
/src/sys/arm/allwinner/
H A Da10_ahci.c61 #define AHCI_BISTAFR 0x00A0
62 #define AHCI_BISTCR 0x00A4
63 #define AHCI_BISTFCTR 0x00A8
64 #define AHCI_BISTSR 0x00AC
65 #define AHCI_BISTDECR 0x00B0
66 #define AHCI_DIAGNR 0x00B4
67 #define AHCI_DIAGNR1 0x00B8
68 #define AHCI_OOBR 0x00BC
69 #define AHCI_PHYCS0R 0x00C0
70 /* Bits 0..17 are a mystery */
[all …]
/src/sys/dev/bnxt/bnxt_re/
H A Dib_verbs.h41 #define BNXT_RE_ROCE_V2_UDP_SPORT 0x8CD1
42 #define BNXT_RE_QP_RANDOM_QKEY 0x81818181
117 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256MB 0x1cUL
508 return 0; in bnxt_re_init_pow2_flag()
512 BNXT_RE_UCNTX_CAP_POW2_DISABLED = 0x1ULL,
513 BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED = 0x2ULL,
533 return 0; in bnxt_re_init_rsvd_wqe_flag()
541 return _is_chip_gen_p5_p7(cctx) ? 0 : BNXT_QPLIB_RESERVED_QP_WRS; in bnxt_re_get_diff()
543 return 0; in bnxt_re_get_diff()
584 return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | in compare_ether_header()
[all …]
/src/sys/contrib/device-tree/Bindings/fpga/
H A Dfpga-region.txt210 bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
218 reg = <0xff706000 0x1000
219 0xffb90000 0x20>;
220 interrupts = <0 175 4>;
225 reg = <0xff400000 0x100000>;
241 reg = <0xff500000 0x10000>;
257 ranges = <0x20000 0xff200000 0x100000>,
258 <0x0 0xc0000000 0x20000000>;
262 reg = <0x10040 0x20>;
272 reg = <0x0 0x10000>;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
107 // immediate value, or 0 if it is not.
110 if (Imm >= 0 && Imm <= 64) in getIntInlineImmEncoding()
116 return 0; in getIntInlineImmEncoding()
121 if (IntImm != 0) in getLit16Encoding()
124 if (Val == 0x3800) // 0.5 in getLit16Encoding()
127 if (Val == 0xB800) // -0.5 in getLit16Encoding()
130 if (Val == 0x3C00) // 1.0 in getLit16Encoding()
133 if (Val == 0xBC00) // -1.0 in getLit16Encoding()
136 if (Val == 0x4000) // 2.0 in getLit16Encoding()
[all …]
H A DAMDGPUInstPrinter.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
53 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
69 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
76 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
81 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
86 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
92 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
106 if (Imm != 0) { in printOffset()
123 if (Imm != 0) { in printFlatOffset()
211 // For th = 0 do not print this field in printTH()
[all …]
/src/sys/arm64/freescale/imx/
H A Dimx8mp_ccm.c350 FIXED(IMX8MP_CLK_DUMMY, "dummy", 0),
359 MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
360 MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
361 MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
362 MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
363 MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
364 MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
365 MUX(IMX8MP_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x84, 0, 2),
366 MUX(IMX8MP_SYS_PLL1_REF_SEL, "sys_pll1_ref_sel", pll_ref_p, 0, 0x94, 0, 2),
367 MUX(IMX8MP_SYS_PLL2_REF_SEL, "sys_pll2_ref_sel", pll_ref_p, 0, 0x104, 0, 2),
[all …]
/src/sys/dev/pms/RefTisa/sat/src/
H A Dsmdefs.h29 #define SM_ROOT_MEM_INDEX 0 /**< the index of dm roo…
41 SM_TIMER_LOCK = 0,
51 #define SATA_ATA_DEVICE 0x01 /**< ATA ATA device ty…
52 #define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device …
53 #define SATA_PM_DEVICE 0x03 /**< ATA PM device typ…
54 #define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device t…
55 #define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without …
56 #define UNKNOWN_DEVICE 0xFF
61 #define PIO_SETUP_DEV_TO_HOST_FIS 0x5F
62 #define REG_DEV_TO_HOST_FIS 0x34
[all …]
/src/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
66 return VersionMajor >= 11 ? 10 : 0; in getVmcntBitShiftLo()
76 return VersionMajor >= 11 ? 0 : 4; in getExpcntBitShift()
97 return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0; in getVmcntBitWidthHi()
102 return VersionMajor >= 12 ? 6 : 0; in getLoadcntBitWidth()
107 return VersionMajor >= 12 ? 6 : 0; in getSamplecntBitWidth()
112 return VersionMajor >= 12 ? 3 : 0; in getBvhcntBitWidth()
117 return VersionMajor >= 12 ? 6 : 0; in getDscntBitWidth()
121 unsigned getDscntBitShift(unsigned VersionMajor) { return 0; } in getDscntBitShift()
125 return VersionMajor >= 10 ? 6 : 0; in getStorecntBitWidth()
[all …]
/src/sys/dev/pms/RefTisa/tisa/sassata/common/
H A Dtddefs.h40 #define agFALSE 0
44 #define agNULL ((void *)0)
72 #define OFF 0
87 #define TD_OPERATION_INITIATOR 0x1
88 #define TD_OPERATION_TARGET 0x2
111 #define TD_CARD_ID_FREE 0
140 #define DEFAULT_OUTBOUND_QUEUE_INTERRUPT_DELAY 0
143 #define DEFAULT_INBOUND_QUEUE_PRIORITY 0
144 #define DEFAULT_QUEUE_OPTION 0
150 #define SAS_NO_DEVICE 0
[all …]
/src/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h60 /* [0x0] */
62 /* [0x4] */
64 /* [0x8] Force init reset. */
66 /* [0xc] Force init reset per DECEI mode. */
68 /* [0x10] */
70 /* [0x14] */
72 /* [0x18] */
74 /* [0x1c] */
76 /* [0x20] */
78 /* [0x24] */
[all …]
/src/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x4a000000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]

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