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/linux-5.10/Documentation/devicetree/bindings/remoteproc/
Dti,k3-r5f-rproc.yaml58 enum: [0, 1]
61 Should be either a value of 1 (LockStep mode) or 0 (Split mode),
82 either of them can be configured to appear at that R5F's address 0x0.
153 enum: [0, 1]
157 either a value of 1 (enabled) or 0 (disabled), default is disabled
162 enum: [0, 1]
166 either a value of 1 (enabled) or 0 (disabled), default is enabled if
171 enum: [0, 1]
174 address 0 (from core's view). Should be either a value of 1 (ATCM
175 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
[all …]
/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-am65.dtsi68 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
69 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
70 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
71 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
72 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
73 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
Dk3-j7200.dtsi39 #size-cells = <0>;
53 cpu0: cpu@0 {
55 reg = <0x000>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
69 reg = <0x001>;
72 i-cache-size = <0xc000>;
75 d-cache-size = <0x8000>;
85 cache-size = <0x100000>;
125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j721e.dtsi40 #size-cells = <0>;
54 cpu0: cpu@0 {
56 reg = <0x000>;
59 i-cache-size = <0xC000>;
62 d-cache-size = <0x8000>;
70 reg = <0x001>;
73 i-cache-size = <0xC000>;
76 d-cache-size = <0x8000>;
86 cache-size = <0x100000>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/linux-5.10/Documentation/devicetree/bindings/watchdog/
Dfaraday,ftwdt010.txt20 reg = <0x41000000 0x1000>;
/linux-5.10/Documentation/devicetree/bindings/pci/
Dhost-generic-pci.yaml94 property. If no "bus-range" is specified, this will be bus 0 (the
153 bus-range = <0x0 0x1>;
156 reg = <0x0 0x40000000 0x0 0x1000000>;
159 ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
160 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
162 #interrupt-cells = <0x1>;
165 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
166 < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
167 <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
168 <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
[all …]
Dcdns,cdns-pcie-host.yaml47 bus-range = <0x0 0xff>;
48 linux,pci-domain = <0>;
49 vendor-id = <0x17cd>;
50 device-id = <0x0200>;
52 reg = <0x0 0xfb000000 0x0 0x01000000>,
53 <0x0 0x41000000 0x0 0x00001000>;
56 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
57 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
58 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
60 #interrupt-cells = <0x1>;
[all …]
Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
/linux-5.10/Documentation/devicetree/bindings/sound/
Dmrvl,pxa-ssp.txt22 reg = <0x41000000 0x40>;
24 clock-names = "pxa27x-ssp.0";
29 ssp_dai0: ssp_dai@0 {
32 #sound-dai-cells = <0>;
/linux-5.10/Documentation/devicetree/bindings/mtd/
Doxnas-nand.txt17 reg = <0x41000000 0x100000>;
21 #size-cells = <0>;
23 nand@0 {
24 reg = <0>;
30 partition@0 {
32 reg = <0x00000000 0x00e00000>;
38 reg = <0x00e00000 0x07200000>;
/linux-5.10/Documentation/devicetree/bindings/serial/
Dmrvl,pxa-ssp.txt23 reg = <0x41000000 0x40>;
26 clock-names = "pxa27x-ssp.0";
34 reg = <0x41700000 0x40>;
45 reg = <0x41900000 0x40>;
47 interrupts = <0>;
56 reg = <0x41a00000 0x40>;
/linux-5.10/arch/arm/boot/dts/
Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
Dexynos4412-smdk4412.dts22 reg = <0x40000000 0x40000000>;
26 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
33 clock-frequency = <0>;
44 #clock-cells = <0>;
70 pinctrl-0 = <&keypad_rows &keypad_cols>;
117 keypad,row = <0>;
129 keypad,row = <0>;
137 samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
144 samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
159 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
Dexynos4210-smdkv310.dts25 reg = <0x40000000 0x80000000>;
29 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
47 #clock-cells = <0>;
68 #size-cells = <0>;
75 reg = <0x50>;
80 reg = <0x52>;
90 pinctrl-0 = <&keypad_rows &keypad_cols>;
94 keypad,row = <0>;
100 keypad,row = <0>;
106 keypad,row = <0>;
[all …]
Ddra74x.dtsi49 reg = <0x41500000 0x100>;
54 reg = <0x48940000 0x4>,
55 <0x48940010 0x4>;
66 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
70 ranges = <0x0 0x48940000 0x20000>;
72 omap_dwc3_4: omap_dwc3_4@0 {
74 reg = <0 0x10000>;
83 reg = <0x10000 0x17000>;
98 reg = <0x41501000 0x4>,
99 <0x41501010 0x4>,
[all …]
Dox820.dtsi19 #size-cells = <0>;
22 cpu@0 {
26 reg = <0>;
39 /* Max 512MB @ 0x60000000 */
40 reg = <0x60000000 0x20000000>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
[all …]
Dexynos4210-origen.dts26 reg = <0x40000000 0x10000000
27 0x50000000 0x10000000
28 0x60000000 0x10000000
29 0x70000000 0x10000000>;
33 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
51 gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
96 clock-frequency = <0>;
107 #clock-cells = <0>;
150 pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
171 pinctrl-0 = <&i2c0_bus>;
[all …]
Dexynos5250-smdk5250.dts24 reg = <0x40000000 0x80000000>;
28 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
71 #clock-cells = <0>;
82 samsung,color-space = <0>;
84 samsung,link-rate = <0x0a>;
88 pinctrl-0 = <&dp_hpd>;
130 reg = <0x50>;
135 reg = <0x09>;
139 pinctrl-0 = <&max77686_irq>;
145 regulator-name = "P1.0V_LDO_OUT1";
[all …]
Dpxa3xx.dtsi6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
14 0)
17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
[all …]
/linux-5.10/arch/arm/include/asm/hardware/
Ddec21285.h9 #define DC21285_PCI_IACK 0x79000000
10 #define DC21285_ARMCSR_BASE 0x42000000
11 #define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
12 #define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
13 #define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
14 #define DC21285_FLASH 0x41000000
15 #define DC21285_PCI_IO 0x7c000000
16 #define DC21285_PCI_MEM 0x80000000
25 #define CSR_PCICMD DC21285_IO(0x0004)
26 #define CSR_CLASSREV DC21285_IO(0x0008)
[all …]
/linux-5.10/arch/arm/configs/
Dexynos_defconfig16 CONFIG_ZBOOT_ROM_TEXT=0x0
17 CONFIG_ZBOOT_ROM_BSS=0x0
20 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/li…
/linux-5.10/arch/arm/mach-footbridge/
Dcommon.c36 mem_fclk_21285 = simple_strtoul(arg, NULL, 0); in early_fclk()
37 return 0; in early_fclk()
45 return 0; in parse_tag_memclk()
55 IRQ_MASK_UART_RX, /* 0 */
103 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { in __fb_init_irq()
199 soft_restart(0x41000000); in footbridge_restart()
216 *CSR_TIMER4_LOAD = 0x2; in footbridge_restart()
217 *CSR_TIMER4_CLR = 0; in footbridge_restart()
226 return *CSR_PCISDRAMBASE & 0xfffffff0; in fb_bus_sdram_offset()
/linux-5.10/arch/arm/kernel/
Dhead.S31 * the least significant 16 bits to be 0x8000, but we could probably
32 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
35 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
36 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
41 #define PG_DIR_SIZE 0x5000
44 #define PG_DIR_SIZE 0x4000
61 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
65 * 0xc0008000, you call this at __pa(0xc0008000).
91 mrc p15, 0, r9, c0, c0 @ get processor id
93 movs r10, r5 @ invalid processor (r5=0)?
[all …]
/linux-5.10/sound/pci/mixart/
Dmixart_core.h15 MSG_CONNECTOR_GET_AUDIO_INFO = 0x050008,
16 MSG_CONNECTOR_GET_OUT_AUDIO_LEVEL = 0x050009,
17 MSG_CONNECTOR_SET_OUT_AUDIO_LEVEL = 0x05000A,
19 MSG_CONSOLE_MANAGER = 0x070000,
20 MSG_CONSOLE_GET_CLOCK_UID = 0x070003,
22 MSG_PHYSICALIO_SET_LEVEL = 0x0F0008,
24 MSG_STREAM_ADD_INPUT_GROUP = 0x130000,
25 MSG_STREAM_ADD_OUTPUT_GROUP = 0x130001,
26 MSG_STREAM_DELETE_GROUP = 0x130004,
27 MSG_STREAM_START_STREAM_GRP_PACKET = 0x130006,
[all …]
/linux-5.10/arch/arm/mach-pxa/
Ddevices.c54 [0] = {
55 .start = 0x41100000,
56 .end = 0x41100fff,
66 static u64 pxamci_dmamask = 0xffffffffUL;
70 .id = 0,
73 .coherent_dma_mask = 0xffffffff,
95 [0] = {
96 .start = 0x40600000,
97 .end = 0x4060ffff,
107 static u64 udc_dma_mask = ~(u32)0;
[all …]

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