Searched +full:0 +full:x40012000 (Results 1 – 4 of 4) sorted by relevance
13 * 0xff800000 0x40000000 1MB X-Bus14 * 0xff000000 0x7c000000 1MB PCI I/O space15 * 0xfe000000 0x42000000 1MB CSR16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)17 * 0xfc000000 0x79000000 1MB PCI IACK/special space18 * 0xfb000000 0x7a000000 16MB PCI Config type 119 * 0xfa000000 0x7b000000 16MB PCI Config type 020 * 0xf9000000 0x50000000 1MB Cache flush21 * 0xf0000000 0x80000000 16MB ISA memory30 #define XBUS_SIZE 0x00100000[all …]
90 const: 0199 "^adc@[0-9]+$":215 - 0x0: ADC1216 - 0x100: ADC2217 - 0x200: ADC3 (stm32f4 only)226 - 0 for adc@0254 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4255 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and264 <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.275 minimum: 0[all …]
58 #clock-cells = <0>;60 clock-frequency = <0>;64 #clock-cells = <0>;70 #clock-cells = <0>;76 #clock-cells = <0>;78 clock-frequency = <0>;85 reg = <0x1fff7800 0x400>;89 reg = <0x22c 0x2>;92 reg = <0x22e 0x2>;98 reg = <0x40000000 0x400>;[all …]
16 #size-cells = <0>;18 cpu0: cpu@0 {22 reg = <0>;42 reg = <0xa0021000 0x1000>,43 <0xa0022000 0x2000>;57 #clock-cells = <0>;63 #clock-cells = <0>;69 #clock-cells = <0>;75 #clock-cells = <0>;81 #clock-cells = <0>;[all …]