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/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm4906-tplink-archer-c2300-v1.dts13 memory@0 {
15 reg = <0x00 0x00 0x00 0x20000000>;
24 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
134 port@0 {
169 #size-cells = <0>;
176 partition@0 {
178 reg = <0x0 0x100000>;
183 reg = <0x100000 0x3900000>;
188 reg = <0x3a00000 0x3900000>;
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sc7280-lpasscorecc.yaml146 reg = <0x3300000 0x30000>,
147 <0x32a9000 0x1000>;
164 reg = <0x3c00000 0x28>;
178 reg = <0x3900000 0x50000>;
193 reg = <0x3380000 0x30000>;
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8026-asus-sparrow.dts17 qcom,msm-id = <199 0x20000>;
22 reg = <0x02f00000 0x100000>;
26 reg = <0x3100000 0x200000>;
30 reg = <0x3300000 0x600000>;
34 reg = <0x3900000 0x1400000>;
38 reg = <0x4d00000 0x1b00000>;
42 reg = <0x7f00000 0x100000>;
58 pinctrl-0 = <&wlan_regulator_default_state>;
70 pinctrl-0 = <&blsp1_uart1_default_state>;
77 pinctrl-0 = <&bluetooth_default_state>;
[all …]
H A Dqcom-apq8026-huawei-sturgeon.dts18 qcom,msm-id = <199 0x20000>;
23 reg = <0x02f00000 0x100000>;
28 reg = <0x3100000 0x200000>;
33 reg = <0x3300000 0x600000>;
38 reg = <0x3900000 0x1400000>;
43 reg = <0x4d00000 0x1b00000>;
48 reg = <0x7f00000 0x100000>;
64 pinctrl-0 = <&wlan_regulator_default_state>;
79 reg = <0x5a>;
87 pinctrl-0 = <&vibrator_default_state>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc8308_p1m.dts25 #size-cells = <0>;
27 PowerPC,8308@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x08000000>; // 128MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
53 ranges = <0x0 0x0 0xfc000000 0x04000000
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcm2290.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
68 reg = <0x0 0x1>;
69 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6350.dtsi35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6115.dtsi34 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
69 reg = <0x0 0x1>;
70 clocks = <&cpufreq_hw 0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
90 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_nx.c15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define BLOCK_PROTECT_BITS 0x0F
[all …]
/linux/drivers/scsi/qla4xxx/
H A Dql4_nx.c18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
[all …]