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/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x500
[all...]
/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power9-dual.dtsi5 cfam@0,0 {
6 reg = <0 0>;
9 chip-id = <0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
20 #size-cells = <0>;
[all...]
H A Dibm-power11-quad.dtsi126 #size-cells = <0>;
129 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
131 cfam@0,0 {
132 reg = <0 0>;
135 chip-id = <0>;
139 reg = <0x1000 0x400>;
144 reg = <0x180
[all...]
H A Daspeed-bmc-opp-palmetto.dts17 reg = <0x40000000 0x20000000>;
27 reg = <0x5f000000 0x01000000>; /* 16M */
31 reg = <0x5ee00000 0x00200000>;
37 reg = <0x5C000000 0x02000000>; /* 32MB */
60 #size-cells = <0>;
69 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIG
[all...]
/linux/Documentation/devicetree/bindings/fsi/
H A Dibm,p9-fsi-controller.yaml35 reg = <0x3400 0x400>;
37 #size-cells = <0>;
39 cfam@0,0 {
40 reg = <0 0>;
43 chip-id = <0>;
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp233.dtsi28 #power-domain-cells = <0>;
48 reg = <0x482d0000 0x4000>;
70 st,syscon = <&syscfg 0x3400>;
89 snps,blen = <0 0 0 0 16 8 4>;
90 snps,rd_osr_lmt = <0x
[all...]
H A Dstm32mp253.dtsi28 #power-domain-cells = <0>;
48 reg = <0x482d0000 0x4000>;
70 st,syscon = <&syscfg 0x3400>;
89 snps,blen = <0 0 0 0 16 8 4>;
90 snps,rd_osr_lmt = <0x
[all...]
/linux/include/dt-bindings/pinctrl/
H A Ddra.h13 #define MUX_MODE0 0x0
14 #define MUX_MODE1 0x1
15 #define MUX_MODE2 0x2
16 #define MUX_MODE3 0x3
17 #define MUX_MODE4 0x4
18 #define MUX_MODE5 0x5
19 #define MUX_MODE6 0x6
20 #define MUX_MODE7 0x7
21 #define MUX_MODE8 0x8
22 #define MUX_MODE9 0x
[all...]
/linux/drivers/soc/vt8500/
H A Dwmt-socinfo.c19 { "VT8420", 0x3300 },
20 { "VT8430", 0x3357 },
21 { "VT8500", 0x3400 },
24 { "WM8425", 0x3429 },
25 { "WM8435", 0x3437 },
26 { "WM8440", 0x3451 },
27 { "WM8505", 0x3426 },
28 { "WM8650", 0x3465 },
29 { "WM8750", 0x344
[all...]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
40 #define DP_PHY_LANE_TX_1 0x204
43 #define DP_PHY_LANE_TX_2 0x304
46 #define DP_PHY_LANE_TX_3 0x40
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dpm8998.dtsi34 pm8998_lsid0: pmic@0 {
36 reg = <0x0 SPMI_USID>;
38 #size-cells = <0>;
43 reg = <0x800>;
44 mode-bootloader = <0x2>;
45 mode-recovery = <0x1>;
49 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
57 interrupts = <0x
[all...]
H A Dpmk8350.dtsi13 #define PMK8350_SID 0
21 mode-recovery = <0x01>;
22 mode-bootloader = <0x02>;
31 #size-cells = <0>;
35 reg = <0x1300>, <0x800>;
40 interrupts = <PMK8350_SID 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
47 interrupts = <PMK8350_SID 0x13 0x
[all...]
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,msm8996-qmp-pcie-phy.yaml57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x13
[all...]
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x340
[all...]
/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom-spmi-adc-tm-hc.yaml30 const: 0
54 "^([-a-z0-9]*)@[0-7]$":
62 minimum: 0
75 channel will be calibrated with 0V and 1.25V reference channels,
80 enum: [0, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 6000, 8000, 10000]
118 #size-cells = <0>;
122 reg = <0x3100>;
124 #size-cells = <0>;
135 reg = <0x3400>;
[all...]
H A Dqcom-spmi-adc-tm5.yaml33 const: 0
59 "^([-a-z0-9]*)@[0-7]$":
67 minimum: 0
80 channel will be calibrated with 0V and 1.25V reference channels,
139 "^([-a-z0-9]*)@[0-7]$":
171 #size-cells = <0>;
175 reg = <0x3100>;
177 #size-cells = <0>;
191 reg = <0x3500>;
192 interrupts = <0x
[all...]
/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx8qxp-dc-blit-engine.yaml56 (4:4:4, 4:2:2, 4:2:0).
82 "^blitblend@[0-9a-f]+$":
90 "^clut@[0-9a-f]+$":
98 "^fetchdecode@[0-9a-f]+$":
106 "^fetcheco@[0-9a-f]+$":
114 "^fetchwarp@[0-9a-f]+$":
122 "^filter@[0-9a-f]+$":
130 "^hscaler@[0-9a-f]+$":
138 "^matrix@[0-9a-f]+$":
146 "^rop@[0
[all...]
/linux/sound/soc/codecs/
H A Drt721-sdca-sdw.h15 { 0x202d, 0x00 },
16 { 0x2f01, 0x00 },
17 { 0x2f02, 0x09 },
18 { 0x2f03, 0x08 },
19 { 0x2f04, 0x0
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_d.h26 #define ixCLIENT0_BM 0x0220
27 #define ixCLIENT0_CD0 0x0210
28 #define ixCLIENT0_CD1 0x0214
29 #define ixCLIENT0_CD2 0x0218
30 #define ixCLIENT0_CD3 0x021C
31 #define ixCLIENT0_CK0 0x0200
32 #define ixCLIENT0_CK1 0x0204
33 #define ixCLIENT0_CK2 0x0208
34 #define ixCLIENT0_CK3 0x020C
35 #define ixCLIENT0_K0 0x01F
[all...]
H A Doss_2_4_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe0
[all...]
H A Doss_3_0_1_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe0
[all...]
/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x53
[all...]
/linux/arch/alpha/kernel/
H A Dsys_nautilus.c75 dev->bus->self && dev->bus->self->device == 0x700f) in nautilus_map_irq()
92 pci_bus_read_config_byte(bus, 0x38, 0x43, &t8); in nautilus_kill_arch()
93 pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80); in nautilus_kill_arch()
94 outb(1, 0x92); in nautilus_kill_arch()
95 outb(0, 0x92); in nautilus_kill_arch()
102 off = 0x200 in nautilus_kill_arch()
[all...]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569si-post.dtsi39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
43 /* controller at 0xa000 */
49 bus-range = <0 255>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
54 pcie@0 {
55 reg = <0
[all...]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dga102.c39 u32 invalid[] = { 0, 0, 0, 0 }, *color; in ga102_gr_zbc_clear_color()
46 nvkm_mask(device, 0x41bcb4, 0x0000001f, zbc); in ga102_gr_zbc_clear_color()
47 nvkm_wr32(device, 0x41bcec, color[0]); in ga102_gr_zbc_clear_color()
48 nvkm_wr32(device, 0x41bcf0, color[1]); in ga102_gr_zbc_clear_color()
49 nvkm_wr32(device, 0x41bcf in ga102_gr_zbc_clear_color()
[all...]

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