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/qemu/tests/qemu-iotests/
H A D02425 seq=`basename $0`
41 trap "_cleanup; exit \$status" 0 1 2 3 15
71 io_pattern writev 0 $CLUSTER_SIZE $((2 * CLUSTER_SIZE)) 8 0x11
79 io_pattern writev 0 $((2 * CLUSTER_SIZE)) $((4 * CLUSTER_SIZE)) 4 0x22
88 io_pattern writev 0 $((4 * CLUSTER_SIZE)) 0 1 0x33
89 io_pattern writev $((8 * CLUSTER_SIZE)) $((4 * CLUSTER_SIZE)) 0 1 0x33
93 io_pattern readv $((0 * CLUSTER_SIZE)) $CLUSTER_SIZE 0 1 0x33
94 io_pattern readv $((1 * CLUSTER_SIZE)) $CLUSTER_SIZE 0 1 0x33
95 io_pattern readv $((2 * CLUSTER_SIZE)) $CLUSTER_SIZE 0 1 0x33
96 io_pattern readv $((3 * CLUSTER_SIZE)) $CLUSTER_SIZE 0 1 0x33
[all …]
H A D024.out5 === IO: pattern 0x11
6 wrote 65536/65536 bytes at offset 0
25 === IO: pattern 0x22
26 wrote 131072/131072 bytes at offset 0
37 === IO: pattern 0x33
38 wrote 262144/262144 bytes at offset 0
40 === IO: pattern 0x33
45 === IO: pattern 0x33
46 read 65536/65536 bytes at offset 0
48 === IO: pattern 0x33
[all …]
H A D12225 seq="$(basename $0)"
37 trap "_cleanup; exit \$status" 0 1 2 3 15
49 $QEMU_IO -c "write -P 0x11 0 64M" "$TEST_IMG".base 2>&1 | _filter_qemu_io | _filter_testdir
57 $QEMU_IO -c "write -P 0x22 0 3M" "$TEST_IMG" 2>&1 | _filter_qemu_io | _filter_testdir
69 $QEMU_IO -c "write -P 0 0 3M" "$TEST_IMG" 2>&1 | _filter_qemu_io | _filter_testdir
72 $QEMU_IO -c "read -P 0 0 3M" "$TEST_IMG".orig 2>&1 | _filter_qemu_io | _filter_testdir
75 $QEMU_IO -c "read -P 0 0 3M" "$TEST_IMG".orig 2>&1 | _filter_qemu_io | _filter_testdir
77 $QEMU_IO -c "write -z 0 3M" "$TEST_IMG" 2>&1 | _filter_qemu_io | _filter_testdir
80 $QEMU_IO -c "read -P 0 0 3M" "$TEST_IMG".orig 2>&1 | _filter_qemu_io | _filter_testdir
83 $QEMU_IO -c "read -P 0 0 3M" "$TEST_IMG".orig 2>&1 | _filter_qemu_io | _filter_testdir
[all …]
H A D07325 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
56 $QEMU_IO -c "write -P 0xa5 0 $size" "$TEST_IMG.base" | _filter_qemu_io
61 $QEMU_IO -c "write -P 0x11 0 0x10000" "$TEST_IMG" | _filter_qemu_io
62 $QEMU_IO -c "write -P 0x11 0x10000 0x10000" "$TEST_IMG.base" | _filter_qemu_io
64 $QEMU_IO -c "read -P 0x11 0 0x20000" "$TEST_IMG" | _filter_qemu_io
69 $QEMU_IO -c "write -P 0x22 0x20000 0x10000" "$TEST_IMG" | _filter_qemu_io
70 $QEMU_IO -c "write -c -P 0x22 0x30000 0x10000" "$TEST_IMG" | _filter_qemu_io
72 $QEMU_IO -c "read -P 0x22 0x20000 0x20000" "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c "write -P 0x33 0x40000 0x20000" "$TEST_IMG" | _filter_qemu_io
[all …]
H A D22322 seq="$(basename $0)"
34 trap "_cleanup; exit \$status" 0 1 2 3 15
70 $QEMU_IO -c 'w -P 0x11 1M 2M' "$TEST_IMG" | _filter_qemu_io
106 $QEMU_IO -c 'w -P 0x22 512 512' -c 'w -P 0x33 2M 2M' "$TEST_IMG" \
174 $QEMU_IO -r -c 'r -P 0x22 512 512' -c 'r -P 0 512k 512k' -c 'r -P 0x11 1m 1m' \
175 -c 'r -P 0x33 2m 2m' --image-opts "$IMG" | _filter_qemu_io
234 status=0
/qemu/tests/tcg/riscv64/
H A Dtest-aes.c11 asm(".insn r 0x33, 0x0, 0x19, %0, %2, %3\n\t" in test_SB_SR()
12 ".insn r 0x33, 0x0, 0x19, %1, %3, %2" in test_SB_SR()
13 : "=&r"(o8[0]), "=&r"(o8[1]) : "r"(i8[0]), "r"(i8[1])); in test_SB_SR()
29 asm(".insn r 0x33, 0x0, 0x1b, %0, %2, %3\n\t" in test_SB_SR_MC_AK()
30 ".insn r 0x33, 0x0, 0x1b, %1, %3, %2\n\t" in test_SB_SR_MC_AK()
31 "xor %0,%0,%4\n\t" in test_SB_SR_MC_AK()
33 : "=&r"(o8[0]), "=&r"(o8[1]) in test_SB_SR_MC_AK()
34 : "r"(i8[0]), "r"(i8[1]), "r"(k8[0]), "r"(k8[1])); in test_SB_SR_MC_AK()
44 asm(".insn r 0x33, 0x0, 0x1d, %0, %2, %3\n\t" in test_ISB_ISR()
45 ".insn r 0x33, 0x0, 0x1d, %1, %3, %2" in test_ISB_ISR()
[all …]
/qemu/tests/tcg/hexagon/
H A Dhvx_histogram_input.h18 { 0x26, 0x32, 0x2e, 0x2e, 0x2d, 0x2c, 0x2d, 0x2d,
19 0x2c, 0x2e, 0x31, 0x33, 0x36, 0x39, 0x3b, 0x3f,
20 0x42, 0x46, 0x4a, 0x4c, 0x51, 0x53, 0x53, 0x54,
21 0x56, 0x57, 0x58, 0x57, 0x56, 0x52, 0x51, 0x4f,
22 0x4c, 0x49, 0x47, 0x42, 0x3e, 0x3b, 0x38, 0x35,
23 0x33, 0x30, 0x2e, 0x2c, 0x2b, 0x2a, 0x2a, 0x28,
24 0x28, 0x27, 0x27, 0x28, 0x29, 0x2a, 0x2c, 0x2e,
25 0x2f, 0x33, 0x36, 0x38, 0x3c, 0x3d, 0x40, 0x42,
26 0x43, 0x42, 0x43, 0x44, 0x43, 0x41, 0x40, 0x3b,
27 0x3b, 0x3a, 0x38, 0x35, 0x32, 0x2f, 0x2c, 0x29,
[all …]
/qemu/tests/unit/
H A Dtest-replication.c44 #define NOT_DONE 0x7fffffff
70 memset(pattern_buf, 0x00, count); in test_blk_read()
76 blk_aio_preadv(blk, offset, &qiov, 0, blk_rw_done, &async_ret); in test_blk_read()
82 g_assert(async_ret != 0); in test_blk_read()
84 g_assert(async_ret == 0); in test_blk_read()
87 cmp_buf, pattern_count) <= 0); in test_blk_read()
107 memset(pattern_buf, 0x00, count); in test_blk_write()
113 blk_aio_pwritev(blk, offset, &qiov, 0, blk_rw_done, &async_ret); in test_blk_write()
119 g_assert(async_ret != 0); in test_blk_write()
121 g_assert(async_ret == 0); in test_blk_write()
[all …]
H A Dtest-crypto-der.c27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
46 "\x00\xd1\x75\xaf\x4b\xc6\x1a\xb0\x98\x14\x42\xae\x33\xf3\x44\xde"
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
68 "\xa3\xfc\x33\x55\x89\xa9\xc3\xea\x5b\x2e\x31\x06\xf8\xcb\x9e\x6e"
95 "\x23\x8a\x48\x50\x1d\x33\x6a\x86\x46\x69\xed\x54\x65\x6b\x9e\xab"
97 "\xe0\xa8\xc7\xb9\x38\x74\x24\x51\x33\xf0\x39\x54\x6c\x11\xae\xc2"
115 "\x6d\x0b\x12\x0b\xc9\x6d\x59\xfc\x33\x03\x36\x01\x12\x09\x72\x74"
135 "\x77\x85\x33\x92\x9a\xff\x95\xba\x8c\xcd\xa7\x89\xc2\x46\x00\x21"
146 "\x88\x14\x33\xe6\xbc\xca\x6b\x88\x90\x57\x3b\x0c\xa3\x6e\x47\xdf"
151 "\x30\x53" /* SEQUENCE, offset 0, length 83 */
[all …]
H A Dtest-crypto-akcipher.c29 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
30 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
31 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
32 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
33 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
34 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
35 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
36 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
37 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
38 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
H A Dtest-crypto-pbkdf.c64 "\x33\xec\xc0\xe2\xe1\xf7\x08\x37",
221 .key = "pass\0word",
223 .salt = "sa\0lt",
237 .nkey = 0,
289 "\x49\x33\x35\xa6\xc3\x83\xae\x23"
324 "\xe4\x01\x0d\x6f\xb5\x33\xc8\xbd"
344 #if 0
367 return '0' + i; in hex()
378 for (i = 0; i < len; i++) { in hex_string()
379 hexstr[i * 2] = hex((bytes[i] >> 4) & 0xf); in hex_string()
[all …]
H A Dtest-crypto-xts.c46 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
47 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
48 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
49 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
50 0,
52 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
53 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
54 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
55 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
56 { 0x91, 0x7c, 0xf6, 0x9e, 0xbd, 0x68, 0xb2, 0xec,
[all …]
/qemu/pc-bios/keymaps/
H A Dsl3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
17 Super_L 0xdb
[all …]
H A Dsv1 map 0x0000041d
3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
[all …]
H A Dno11 # 0: Shift
33 # evdev 1 (0x1), QKeyCode "esc", number 0x1
34 Escape 0x01
36 # evdev 2 (0x2), QKeyCode "1", number 0x2
37 1 0x02
38 exclam 0x02 shift
39 exclamdown 0x02 altgr
40 onesuperior 0x02 shift altgr
42 # evdev 3 (0x3), QKeyCode "2", number 0x3
43 2 0x03
[all …]
H A Dpl11 # 0: Shift
33 # evdev 1 (0x1), QKeyCode "esc", number 0x1
34 Escape 0x01
36 # evdev 2 (0x2), QKeyCode "1", number 0x2
37 1 0x02
38 exclam 0x02 shift
39 notequal 0x02 altgr
40 exclamdown 0x02 shift altgr
42 # evdev 3 (0x3), QKeyCode "2", number 0x3
43 2 0x03
[all …]
/qemu/util/
H A Dcpuinfo-riscv.c74 if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0 in cpuinfo_init()
75 && pair.key >= 0) { in cpuinfo_init()
76 info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; in cpuinfo_init()
77 info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; in cpuinfo_init()
78 info |= pair.value & RISCV_HWPROBE_EXT_ZBS ? CPUINFO_ZBS : 0; in cpuinfo_init()
81 info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; in cpuinfo_init()
85 info |= pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : 0; in cpuinfo_init()
87 info |= pair.value & RISCV_HWPROBE_EXT_ZVE64X ? CPUINFO_ZVE64X : 0; in cpuinfo_init()
102 memset(&sa_new, 0, sizeof(sa_new)); in cpuinfo_init()
109 got_sigill = 0; in cpuinfo_init()
[all …]
/qemu/hw/arm/
H A Daspeed_eeprom.c12 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
13 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
14 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
15 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
16 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
17 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
18 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
19 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
20 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
21 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x54, 0x69, 0x6f, 0x67, 0x61,
[all …]
/qemu/tests/qtest/
H A Dlsm303dlhc-mag-test.c19 #define LSM303DLHC_MAG_REG_CRA 0x00
20 #define LSM303DLHC_MAG_REG_CRB 0x01
21 #define LSM303DLHC_MAG_REG_OUT_X_H 0x03
22 #define LSM303DLHC_MAG_REG_OUT_Z_H 0x05
23 #define LSM303DLHC_MAG_REG_OUT_Y_H 0x07
24 #define LSM303DLHC_MAG_REG_IRC 0x0C
25 #define LSM303DLHC_MAG_REG_TEMP_OUT_H 0x31
57 g_assert_cmphex(i2c_get8(i2cdev, LSM303DLHC_MAG_REG_CRB), ==, 0x20); in send_and_receive()
97 /* Read raw temperature registers with temp disabled (CRA = 0x10) */ in send_and_receive()
99 g_assert_cmphex(value, ==, 0); in send_and_receive()
[all …]
/qemu/ebpf/
H A Drss.bpf.skeleton.h146 s->maps[0].name = "tap_rss_map_configurations"; in rss_bpf__create_skeleton()
147 s->maps[0].map = &obj->maps.tap_rss_map_configurations; in rss_bpf__create_skeleton()
164 s->progs[0].name = "tun_rss_steering_prog"; in rss_bpf__create_skeleton()
165 s->progs[0].prog = &obj->progs.tun_rss_steering_prog; in rss_bpf__create_skeleton()
166 s->progs[0].link = &obj->links.tun_rss_steering_prog; in rss_bpf__create_skeleton()
171 return 0; in rss_bpf__create_skeleton()
180 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
181 \0\0\0\0\0\0\0\0\0\0\0\xb0\x4b\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\ in rss_bpf__elf_bytes()
182 \x01\0\x7b\x1a\x48\xff\0\0\0\0\xb7\x09\0\0\0\0\0\0\x63\x9a\x54\xff\0\0\0\0\xbf\ in rss_bpf__elf_bytes()
183 \xa7\0\0\0\0\0\0\x07\x07\0\0\x54\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
[all …]
/qemu/tests/bench/
H A Dtest_akcipher_keys.c.inc12 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
13 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
14 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
15 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
16 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
17 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
18 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
19 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
20 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
21 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
/qemu/include/hw/sensor/
H A Disl_pmbus_vr.h30 #define ISL_CAPABILITY_DEFAULT 0x40
31 #define ISL_OPERATION_DEFAULT 0x80
32 #define ISL_ON_OFF_CONFIG_DEFAULT 0x16
33 #define ISL_VOUT_MODE_DEFAULT 0x40
34 #define ISL_VOUT_COMMAND_DEFAULT 0x0384
35 #define ISL_VOUT_MAX_DEFAULT 0x08FC
36 #define ISL_VOUT_MARGIN_HIGH_DEFAULT 0x0640
37 #define ISL_VOUT_MARGIN_LOW_DEFAULT 0xFA
38 #define ISL_VOUT_TRANSITION_RATE_DEFAULT 0x64
39 #define ISL_VOUT_OV_FAULT_LIMIT_DEFAULT 0x076C
[all …]
/qemu/hw/s390x/
H A Dvirtio-ccw.h23 #define VIRTIO_CCW_CU_TYPE 0x3832
24 #define VIRTIO_CCW_CHPID_TYPE 0x32
26 #define CCW_CMD_SET_VQ 0x13
27 #define CCW_CMD_VDEV_RESET 0x33
28 #define CCW_CMD_READ_FEAT 0x12
29 #define CCW_CMD_WRITE_FEAT 0x11
30 #define CCW_CMD_READ_CONF 0x22
31 #define CCW_CMD_WRITE_CONF 0x21
32 #define CCW_CMD_WRITE_STATUS 0x31
33 #define CCW_CMD_SET_IND 0x43
[all …]
/qemu/disas/
H A Dsparc.c49 SPARC_OPCODE_ARCH_V6 = 0,
178 0 32/64 bit immediate for set or setx (v9) insns
185 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
186 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
187 #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
188 #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
189 #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
191 #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
195 #define DISP30(x) ((x) & 0x3fffffff)
196 #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
[all …]
/qemu/linux-user/x86_64/
H A Dtarget_syscall.h4 #define __USER_CS (0x33)
5 #define __USER_DS (0x2B)
45 #if 0 // Redefine this
99 #define TARGET_ARCH_SET_GS 0x1001
100 #define TARGET_ARCH_SET_FS 0x1002
101 #define TARGET_ARCH_GET_FS 0x1003
102 #define TARGET_ARCH_GET_GS 0x1004

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