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/linux/drivers/net/wireless/intel/iwlwifi/cfg/
H A Dax210.c19 #define IWL_AX210_SMEM_OFFSET 0x400000
20 #define IWL_AX210_SMEM_LEN 0xD0000
35 .mac_addr_from_csr = 0x380,
36 .min_umac_error_event_table = 0x400000,
37 .d3_debug_data_base_addr = 0x401000,
50 .gp2_reg_addr = 0xd02c68,
59 .mask = 0xffffffff,
75 .umac_prph_offset = 0x300000,
85 .umac_prph_offset = 0x300000,
97 .umac_prph_offset = 0x300000,
[all …]
H A Dbz.c19 #define IWL_BZ_SMEM_OFFSET 0x400000
20 #define IWL_BZ_SMEM_LEN 0xD0000
40 .mac_addr_from_csr = 0x30,
41 .min_umac_error_event_table = 0xD0000,
42 .d3_debug_data_base_addr = 0x401000,
55 .gp2_reg_addr = 0xd02c68,
64 .mask = 0xffffffff,
88 .umac_prph_offset = 0x300000,
99 .umac_prph_offset = 0x300000,
/linux/drivers/soc/qcom/
H A Dqcom_gsbi.c17 #define GSBI_CTRL_REG 0x0000
21 #define TCSR_ADM_CRCI_BASE 0x70
30 0x000003, 0x00000c, 0x000030, 0x0000c0,
31 0x000300, 0x000c00, 0x003000, 0x00c000,
32 0x030000, 0x0c0000, 0x300000, 0xc00000
35 0x000003, 0x00000c, 0x000030, 0x0000c0,
36 0x000300, 0x000c00, 0x003000, 0x00c000,
37 0x030000, 0x0c0000, 0x300000, 0xc00000
48 0x001800, 0x006000, 0x000030, 0x0000c0,
49 0x000300, 0x000400, 0x000000, 0x000000,
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm8150-pinctrl.yaml65 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
117 reg = <0x03100000 0x300000>,
118 <0x03500000 0x300000>,
119 <0x03900000 0x300000>,
120 <0x03d00000 0x300000>;
123 gpio-ranges = <&tlmm 0 0 176>;
H A Dqcom,qcs615-tlmm.yaml67 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$"
108 reg = <0x03100000 0x300000>,
109 <0x03500000 0x300000>,
110 <0x03c00000 0x300000>;
113 gpio-ranges = <&tlmm 0 0 124>;
H A Dqcom,sm8250-pinctrl.yaml63 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
109 reg = <0x0f100000 0x300000>,
110 <0x0f500000 0x300000>,
111 <0x0f900000 0x300000>;
118 gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
H A Dqcom,sm7150-tlmm.yaml67 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
115 reg = <0x03500000 0x300000>,
116 <0x03900000 0x300000>,
117 <0x03d00000 0x300000>;
120 gpio-ranges = <&tlmm 0 0 120>;
H A Dqcom,sc8180x-tlmm.yaml61 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
108 reg = <0x03100000 0x300000>,
109 <0x03500000 0x700000>,
110 <0x03d00000 0x300000>;
117 gpio-ranges = <&tlmm 0 0 190>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>;
51 compatible = "fsl,sec-v4.0-job-ring";
52 reg = <0x2000 0x1000>;
[all …]
H A Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
52 compatible = "fsl,sec-v5.0-job-ring",
[all …]
H A Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
53 "fsl,sec-v4.0-job-ring";
54 reg = <0x2000 0x1000>;
[all …]
H A Dqoriq-sec5.3-0.dtsi2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
54 "fsl,sec-v5.0-job-ring",
[all …]
H A Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
54 "fsl,sec-v5.0-job-ring",
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-apf28.dts15 reg = <0x40000000 0x08000000>;
21 pinctrl-0 = <&duart_pins_a>;
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
30 partition@0 {
32 reg = <0x0 0x300000>;
37 reg = <0x300000 0x80000>;
42 reg = <0x380000 0x80000>;
47 reg = <0x400000 0x80000>;
52 reg = <0x480000 0x80000>;
57 reg = <0x500000 0x800000>;
[all …]
/linux/arch/mips/boot/dts/ralink/
H A Drt2880.dtsi10 cpu@0 {
16 #address-cells = <0>;
24 reg = <0x300000 0x200000>;
25 ranges = <0x0 0x300000 0x1FFFFF>;
30 sysc: syscon@0 {
32 reg = <0x0 0x100>;
39 reg = <0x200 0x100>;
50 reg = <0x300 0x100>;
55 reg = <0xc00 0x100>;
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05-d02.dts17 memory@0 {
19 reg = <0x0 0x00000000 0x0 0x80000000>;
37 debounce-interval = <0>;
54 ranges = <0 0 0x0 0x90000000 0x08000000>,
55 <1 0 0x0 0x98000000 0x08000000>;
57 nor-flash@0 {
61 reg = <0 0x0 0x08000000>;
64 partition@0 {
66 reg = <0x0 0x300000>;
70 reg = <0x300000 0xa00000>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958625-meraki-mx6x-common.dtsi20 pwms = <&pwm 1 50000 0>;
27 pwms = <&pwm 2 50000 0>;
34 pwms = <&pwm 3 50000 0>;
55 reg = <0x50>;
65 reg = <0x66 0x6>;
72 nand@0 {
74 reg = <0>;
85 partition@0 {
87 reg = <0x0 0x80000>;
93 reg = <0x80000 0x80000>;
[all …]
H A Dbcm53016-meraki-mr32.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>;
61 led-0 {
65 pwms = <&pwm 0 50000 0>;
73 pwms = <&pwm 1 50000 0>;
81 pwms = <&pwm 2 50000 0>;
124 pinctrl-0 = <&pinmux_pwm>;
132 * [ 1.721667] 1 bcm47xxpart partitions found on MTD device brcmnand.0
133 * [ 1.727962] Creating 1 MTD partitions on "brcmnand.0":
134 * [ 1.733117] 0x000000400000-0x000008000000 : "nvram"
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-pogoplug-series-4.dts23 reg = <0x00000000 0x08000000>;
32 pinctrl-0 = <&pmx_button_eject>;
46 pinctrl-0 = <&pmx_led_green &pmx_led_red>;
103 * This PCIE controller has a USB 3.0 XHCI controller at 1,0
115 pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
122 pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
137 partition@0 {
139 reg = <0x00000000 0x200000>;
145 reg = <0x00200000 0x300000>;
150 reg = <0x00500000 0x300000>;
[all …]
H A Dkirkwood-iconnect.dts13 reg = <0x00000000 0x10000000>;
19 linux,initrd-start = <0x4500040>;
20 linux,initrd-end = <0x4800000>;
71 reg = <0x4c>;
81 pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
125 pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
146 partition@0 {
148 reg = <0x0000000 0xc0000>;
153 reg = <0xa0000 0x20000>;
158 reg = <0x100000 0x300000>;
[all …]
H A Darmada-370-seagate-nas-xbay.dtsi11 * TODO: add support for the white SATA LEDs associated with HDD 0 and 1.
23 memory@0 {
25 reg = <0x00000000 0x20000000>; /* 512 MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
44 pinctrl-0 = <&ge0_rgmii_pins>;
52 pinctrl-0 = <&i2c0_pins>;
59 reg = <0x51>;
65 reg = <0x6f>;
97 gpios = <&gpio2 0 GPIO_ACTIVE_HIGH
[all …]
/linux/include/video/
H A Dpmag-ba-fb.h16 #define PMAG_BA_FBMEM 0x000000 /* frame buffer */
17 #define PMAG_BA_BT459 0x200000 /* Bt459 RAMDAC */
18 #define PMAG_BA_IRQ 0x300000 /* IRQ acknowledge */
19 #define PMAG_BA_ROM 0x380000 /* REX option ROM */
20 #define PMAG_BA_BT438 0x380000 /* Bt438 clock chip reset */
21 #define PMAG_BA_SIZE 0x400000 /* address space size */
24 #define BT459_ADDR_LO 0x0 /* address low */
25 #define BT459_ADDR_HI 0x4 /* address high */
26 #define BT459_DATA 0x8 /* data window register */
27 #define BT459_CMAP 0xc /* color map window register */
/linux/drivers/crypto/intel/qat/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.h9 #define ADF_DH895XCC_SRAM_BAR 0
12 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
14 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0
15 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1
16 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2
17 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3
21 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
22 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
26 #define ADF_DH895XCC_ERR_REG_VF2PF_L(vf_src) (((vf_src) & 0x01FFFE00) >> 9)
27 #define ADF_DH895XCC_ERR_MSK_VF2PF_L(vf_mask) (((vf_mask) & 0xFFFF) << 9)
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-t7-a311d2-khadas-vim4.dts18 memory@0 {
20 reg = <0x0 0x0 0x2 0x0>; /* 8 GB */
30 reg = <0x0 0x05000000 0x0 0x300000>;
36 reg = <0x0 0x05300000 0x0 0x2000000>;
45 #clock-cells = <0>;

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