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/linux-5.10/drivers/soc/qcom/ !
Dqcom_gsbi.c17 #define GSBI_CTRL_REG 0x0000
21 #define TCSR_ADM_CRCI_BASE 0x70
30 0x000003, 0x00000c, 0x000030, 0x0000c0,
31 0x000300, 0x000c00, 0x003000, 0x00c000,
32 0x030000, 0x0c0000, 0x300000, 0xc00000
35 0x000003, 0x00000c, 0x000030, 0x0000c0,
36 0x000300, 0x000c00, 0x003000, 0x00c000,
37 0x030000, 0x0c0000, 0x300000, 0xc00000
48 0x001800, 0x006000, 0x000030, 0x0000c0,
49 0x000300, 0x000400, 0x000000, 0x000000,
[all …]
/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/ !
Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/linux-5.10/Documentation/devicetree/bindings/pinctrl/ !
Dqcom,sm8150-pinctrl.txt178 reg = <0x03100000 0x300000>,
179 <0x03500000 0x300000>,
180 <0x03900000 0x300000>,
181 <0x03D00000 0x300000>;
186 gpio-ranges = <&tlmm 0 0 175>;
187 gpio-reserved-ranges = <0 4>, <126 4>;
Dqcom,sm8250-pinctrl.yaml68 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
136 reg = <0x0f100000 0x300000>,
137 <0x0f500000 0x300000>,
138 <0x0f900000 0x300000>;
145 gpio-ranges = <&tlmm 0 0 180>;
Dqcom,sc7180-pinctrl.txt176 reg = <0x3500000 0x300000>,
177 <0x3900000 0x300000>,
178 <0x3D00000 0x300000>;
183 gpio-ranges = <&tlmm 0 0 119>;
184 gpio-reserved-ranges = <0 4>, <106 4>;
/linux-5.10/arch/powerpc/boot/dts/fsl/ !
Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>;
51 compatible = "fsl,sec-v4.0-job-ring";
52 reg = <0x2000 0x1000>;
[all …]
Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
52 compatible = "fsl,sec-v5.0-job-ring",
[all …]
Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
53 "fsl,sec-v4.0-job-ring";
54 reg = <0x2000 0x1000>;
[all …]
Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
54 "fsl,sec-v5.0-job-ring",
[all …]
Dqoriq-sec5.3-0.dtsi2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
54 "fsl,sec-v5.0-job-ring",
[all …]
/linux-5.10/arch/mips/boot/dts/ralink/ !
Drt2880.dtsi8 cpu@0 {
14 #address-cells = <0>;
22 reg = <0x300000 0x200000>;
23 ranges = <0x0 0x300000 0x1FFFFF>;
28 sysc@0 {
30 reg = <0x0 0x100>;
35 reg = <0x200 0x100>;
46 reg = <0x300 0x100>;
51 reg = <0xc00 0x100>;
/linux-5.10/arch/arm/boot/dts/ !
Dimx28-apf28.dts15 reg = <0x40000000 0x08000000>;
22 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
25 partition@0 {
27 reg = <0x0 0x300000>;
32 reg = <0x300000 0x80000>;
37 reg = <0x380000 0x80000>;
42 reg = <0x400000 0x80000>;
47 reg = <0x480000 0x80000>;
52 reg = <0x500000 0x800000>;
57 reg = <0xd00000 0xf300000>;
[all …]
Dpicoxcell-pc7302-pc3x2.dts14 reg = <0x0 0x08000000>;
31 nand: gpio-nand@2,0 {
35 reg = <2 0x0000 0x1000>;
38 <0x00000000 0x80220000>;
40 gpios = <&banka 1 0 /* rdy */
41 &banka 2 0 /* nce */
42 &banka 3 0 /* ale */
43 &banka 4 0 /* cle */
44 0 /* nwp */>;
48 reg = <0x100000 0x80000>;
[all …]
Dpicoxcell-pc7302-pc3x3.dts14 reg = <0x0 0x08000000>;
37 nand: gpio-nand@2,0 {
41 reg = <2 0x0000 0x1000>;
44 <0x00000000 0x80220000>;
46 gpios = <&banka 1 0 /* rdy */
47 &banka 2 0 /* nce */
48 &banka 3 0 /* ale */
49 &banka 4 0 /* cle */
50 0 /* nwp */>;
54 reg = <0x100000 0x80000>;
[all …]
Dkirkwood-pogoplug-series-4.dts23 reg = <0x00000000 0x08000000>;
33 #size-cells = <0>;
34 pinctrl-0 = <&pmx_button_eject>;
48 pinctrl-0 = <&pmx_led_green &pmx_led_red>;
105 * This PCIE controller has a USB 3.0 XHCI controller at 1,0
117 pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
124 pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
139 partition@0 {
141 reg = <0x00000000 0x200000>;
147 reg = <0x00200000 0x300000>;
[all …]
Dbcm53016-meraki-mr32.dts24 reg = <0x00000000 0x08000000>;
51 #size-cells = <0>;
67 pwms = <&pwm 0 50000 0>;
75 pwms = <&pwm 1 50000 0>;
83 pwms = <&pwm 2 50000 0>;
100 #size-cells = <0>;
104 reg = <0x45>;
110 reg = <0x50>;
149 pinctrl-0 = <&pinmux_pwm>;
159 * [ 1.721667] 1 bcm47xxpart partitions found on MTD device brcmnand.0
[all …]
Dkirkwood-iconnect.dts13 reg = <0x00000000 0x10000000>;
19 linux,initrd-start = <0x4500040>;
20 linux,initrd-end = <0x4800000>;
71 reg = <0x4c>;
81 pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
126 #size-cells = <0>;
127 pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
148 partition@0 {
150 reg = <0x0000000 0xc0000>;
155 reg = <0xa0000 0x20000>;
[all …]
Darmada-370-seagate-nas-xbay.dtsi11 * TODO: add support for the white SATA LEDs associated with HDD 0 and 1.
23 memory@0 {
25 reg = <0x00000000 0x20000000>; /* 512 MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
44 pinctrl-0 = <&ge0_rgmii_pins>;
52 pinctrl-0 = <&i2c0_pins>;
59 reg = <0x51>;
65 reg = <0x6f>;
76 #size-cells = <0>;
[all …]
/linux-5.10/arch/arm64/boot/dts/hisilicon/ !
Dhip05-d02.dts17 memory@0 {
19 reg = <0x0 0x00000000 0x0 0x80000000>;
33 #size-cells = <0>;
39 debounce-interval = <0>;
56 ranges = <0 0 0x0 0x90000000 0x08000000>,
57 <1 0 0x0 0x98000000 0x08000000>;
59 nor-flash@0,0 {
63 reg = <0 0x0 0x08000000>;
66 partition@0 {
68 reg = <0x0 0x300000>;
[all …]
/linux-5.10/drivers/staging/rtl8192e/rtl8192e/ !
Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/linux-5.10/include/video/ !
Dpmag-ba-fb.h16 #define PMAG_BA_FBMEM 0x000000 /* frame buffer */
17 #define PMAG_BA_BT459 0x200000 /* Bt459 RAMDAC */
18 #define PMAG_BA_IRQ 0x300000 /* IRQ acknowledge */
19 #define PMAG_BA_ROM 0x380000 /* REX option ROM */
20 #define PMAG_BA_BT438 0x380000 /* Bt438 clock chip reset */
21 #define PMAG_BA_SIZE 0x400000 /* address space size */
24 #define BT459_ADDR_LO 0x0 /* address low */
25 #define BT459_ADDR_HI 0x4 /* address high */
26 #define BT459_DATA 0x8 /* data window register */
27 #define BT459_CMAP 0xc /* color map window register */
/linux-5.10/arch/alpha/include/uapi/asm/ !
Dsetup.h12 #define BOOT_PCB 0x20000000
13 #define BOOT_ADDR 0x20000000
18 #define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
20 #define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
25 #define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
26 #define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
27 #define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
28 #define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
30 #define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
39 #define COMMAND_LINE ((char*)(PARAM + 0x0000))
[all …]
/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ !
Dmarvell,odmi-controller.txt24 ODMI frame. Those SPI interrupts are 0-based,
37 reg = <0x300000 0x4000>,
38 <0x304000 0x4000>,
39 <0x308000 0x4000>,
40 <0x30C000 0x4000>;
/linux-5.10/drivers/staging/rtl8712/ !
Drtl871x_mp_phy_regdef.h37 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
39 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
40 * 3. RF register 0x00-2E
45 * 1. Page1(0x100)
47 #define rPMAC_Reset 0x100
48 #define rPMAC_TxStart 0x104
49 #define rPMAC_TxLegacySIG 0x108
50 #define rPMAC_TxHTSIG1 0x10c
51 #define rPMAC_TxHTSIG2 0x110
52 #define rPMAC_PHYDebug 0x114
[all …]
/linux-5.10/drivers/crypto/qat/qat_dh895xcc/ !
Dadf_dh895xcc_hw_data.h7 #define ADF_DH895XCC_SRAM_BAR 0
11 #define ADF_DH895XCC_TX_RINGS_MASK 0xFF
12 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
14 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0
15 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1
16 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2
17 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3
21 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
22 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
24 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
[all …]

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