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/qemu/tests/qemu-iotests/
H A D031.out8 magic 0x514649fb
10 backing_file_offset 0x0
11 backing_file_size 0x0
14 crypt_method 0
16 l1_table_offset 0x30000
17 refcount_table_offset 0x10000
19 nb_snapshots 0
20 snapshot_offset 0x0
28 magic 0x12345678 (<unknown>)
36 magic 0x514649fb
[all …]
H A D31231 seq=`basename $0`
38 _rm_test_img "$TEST_IMG.0"
44 trap "_cleanup; exit \$status" 0 1 2 3 15
60 TEST_IMG="$TEST_IMG.0" _make_test_img -o cluster_size=64k 10M
66 quorum="$quorum,file.children.0.file.filename=$TEST_IMG.0"
69 quorum="$quorum,file.children.0.driver=$IMGFMT"
87 # Three data regions, the largest one (0x30000) will be picked, end result:
88 # offset 0x10000, length 0x30000 -> data
89 $QEMU_IO -c "write -P 0 $((0x10000)) $((0x10000))" "$TEST_IMG.0" | _filter_qemu_io
90 $QEMU_IO -c "write -P 0 $((0x10000)) $((0x30000))" "$TEST_IMG.1" | _filter_qemu_io
[all …]
H A D061.out6 wrote 131072/131072 bytes at offset 0
8 magic 0x514649fb
10 backing_file_offset 0x0
11 backing_file_size 0x0
14 crypt_method 0
16 l1_table_offset 0x30000
17 refcount_table_offset 0x10000
19 nb_snapshots 0
20 snapshot_offset 0x0
22 compatible_features [0]
[all …]
H A D176.out3 === Test pass snapshot.0 ===
30 0x7ffd0000 0x30000 TEST_DIR/t.IMGFMT.base
32 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
33 0x7ffe0000 0x20000 TEST_DIR/t.IMGFMT.itmd
34 0x83400000 0x200 TEST_DIR/t.IMGFMT.itmd
36 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
37 0x7ffe0000 0x20000 TEST_DIR/t.IMGFMT.itmd
38 0x83400000 0x200 TEST_DIR/t.IMGFMT.itmd
70 0x7ffd0000 0x30000 TEST_DIR/t.IMGFMT.base
72 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
[all …]
H A D097.out3 === Test pass 0 ===
30 0x7ffd0000 0x30000 TEST_DIR/t.IMGFMT.base
32 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
33 0x7ffe0000 0x20000 TEST_DIR/t.IMGFMT.itmd
34 0x83400000 0x200 TEST_DIR/t.IMGFMT.itmd
36 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
37 0x7ffe0000 0x20000 TEST_DIR/t.IMGFMT.itmd
38 0x83400000 0x200 TEST_DIR/t.IMGFMT.itmd
67 0x7ffd0000 0x30000 TEST_DIR/t.IMGFMT.base
69 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
[all …]
H A D303.out2 wrote 1048576/1048576 bytes at offset 0
29 magic 0x514649fb
31 backing_file_offset 0x0
32 backing_file_size 0x0
35 crypt_method 0
37 l1_table_offset 0x30000
38 refcount_table_offset 0x10000
40 nb_snapshots 0
41 snapshot_offset 0x0
44 autoclear_features [0]
[all …]
H A D257.out9 --- Write #0 ---
11 write -P0x49 0x0000000 0x10000
13 write -P0x6c 0x0100000 0x10000
15 write -P0x6f 0x2000000 0x10000
17 write -P0x76 0x3ff0000 0x10000
23 --- Reference Backup #0 ---
35 {"data": {"device": "ref_backup_0", "len": 67108864, "offset": 67108864, "speed": 0, "type": "backu…
44 write -P0x65 0x0000000 0x10000
46 write -P0x77 0x00f8000 0x10000
48 write -P0x72 0x2008000 0x10000
[all …]
H A D274.out2 wrote 2097152/2097152 bytes at offset 0
6 read 1048576/1048576 bytes at offset 0
13 1048576/1048576 bytes allocated at offset 0 bytes
16 0/1048576 bytes allocated at offset 0 bytes
17 0/0 bytes allocated at offset 1 MiB
19 0/1048576 bytes allocated at offset 0 bytes
20 0/1048576 bytes allocated at offset 1 MiB
23 [{ "start": 0, "length": 2097152, "depth": 0, "present": true, "zero": false, "data": true, "compre…
26 0 0x200000 0x50000 TEST_DIR/PID-base
28 [{ "start": 0, "length": 1048576, "depth": 1, "present": true, "zero": false, "data": true, "compre…
[all …]
H A D024.out5 === IO: pattern 0x11
6 wrote 65536/65536 bytes at offset 0
25 === IO: pattern 0x22
26 wrote 131072/131072 bytes at offset 0
37 === IO: pattern 0x33
38 wrote 262144/262144 bytes at offset 0
40 === IO: pattern 0x33
45 === IO: pattern 0x33
46 read 65536/65536 bytes at offset 0
48 === IO: pattern 0x33
[all …]
H A D312.out5 Formatting 'TEST_DIR/t.IMGFMT.0', fmt=IMGFMT size=10485760
65 …, "data": {"device": "virtio0", "len": 10485760, "offset": 10485760, "speed": 0, "type": "mirror"}}
71 …, "data": {"device": "virtio0", "len": 10485760, "offset": 10485760, "speed": 0, "type": "mirror"}}
77 0x10000 0x30000 TEST_DIR/t.IMGFMT.3
78 0x100000 0x10000 TEST_DIR/t.IMGFMT.3
79 0x120000 0x20000 TEST_DIR/t.IMGFMT.3
80 0x200000 0x20000 TEST_DIR/t.IMGFMT.3
H A D07325 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
56 $QEMU_IO -c "write -P 0xa5 0 $size" "$TEST_IMG.base" | _filter_qemu_io
61 $QEMU_IO -c "write -P 0x11 0 0x10000" "$TEST_IMG" | _filter_qemu_io
62 $QEMU_IO -c "write -P 0x11 0x10000 0x10000" "$TEST_IMG.base" | _filter_qemu_io
64 $QEMU_IO -c "read -P 0x11 0 0x20000" "$TEST_IMG" | _filter_qemu_io
69 $QEMU_IO -c "write -P 0x22 0x20000 0x10000" "$TEST_IMG" | _filter_qemu_io
70 $QEMU_IO -c "write -c -P 0x22 0x30000 0x10000" "$TEST_IMG" | _filter_qemu_io
72 $QEMU_IO -c "read -P 0x22 0x20000 0x20000" "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c "write -P 0x33 0x40000 0x20000" "$TEST_IMG" | _filter_qemu_io
[all …]
H A D06025 seq="$(basename $0)"
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 rt_offset=65536 # 0x10000 (XXX: just an assumption)
61 rb_offset=131072 # 0x20000 (XXX: just an assumption)
62 l1_offset=196608 # 0x30000 (XXX: just an assumption)
63 l2_offset=262144 # 0x40000 (XXX: just an assumption)
64 l2_offset_after_snapshot=524288 # 0x80000 (XXX: just an assumption)
86 $QEMU_IO -c "$OPEN_RW" -c "write -P 0x2a 0 512" | _filter_qemu_io
95 $QEMU_IO -c "$OPEN_RW" -c "read 0 512" 2>&1 | _filter_qemu_io \
100 $QEMU_IO -c "$OPEN_RO" -c "read 0 512" | _filter_qemu_io
[all …]
/qemu/tests/unit/
H A Dtest-resv-mem.c16 #define DEBUG 0
22 int i = 0; in print_ranges()
31 printf("%s rev[%i] = [0x%"PRIx64",0x%"PRIx64"]\n", in print_ranges()
95 in = insert_sorted_range(in, 0x10000, UINT64_MAX); in check_range_reverse_array()
96 expected = insert_sorted_range(expected, 0x0, 0xFFFF); in check_range_reverse_array()
97 run_range_inverse_array("test1", &in, &expected, 0x0, UINT64_MAX); in check_range_reverse_array()
101 in = insert_sorted_range(in, 0x10000, 0xFFFFFFFFFFFF); in check_range_reverse_array()
102 expected = insert_sorted_range(expected, 0x0, 0xFFFF); in check_range_reverse_array()
103 expected = insert_sorted_range(expected, 0x1000000000000, UINT64_MAX); in check_range_reverse_array()
104 run_range_inverse_array("test1", &in, &expected, 0x0, UINT64_MAX); in check_range_reverse_array()
[all …]
/qemu/include/hw/pci-host/
H A Dq35.h80 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
81 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
84 #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
86 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50
88 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
89 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
92 #define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000
93 #define MCH_HOST_BRIDGE_F_SMBASE 0x9c
94 #define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff
95 #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01
[all …]
/qemu/tests/qtest/
H A Daspeed-hace-utils.c22 static const uint8_t test_vector[3] = {0x61, 0x62, 0x63};
25 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49,
26 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2,
27 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a,
28 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd,
29 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f,
30 0xa5, 0x4c, 0xa4, 0x9f};
33 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69,
34 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63,
35 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b,
[all …]
H A Dq35-test.c42 .extended_tseg_mbytes = 0,
47 .extended_tseg_mbytes = 0,
52 .extended_tseg_mbytes = 0,
93 pcidev = qpci_device_find(pcibus, 0); in test_smram_lock()
144 pcidev = qpci_device_find(pcibus, 0); in test_tseg_size()
167 * byte in the TSEG always reads as 0xff. in test_tseg_size()
171 g_assert_cmpint(qtest_readb(qts, ram_offs), ==, 0); in test_tseg_size()
176 g_assert_cmpint(qtest_readb(qts, ram_offs), ==, 0xff); in test_tseg_size()
178 g_assert_cmpint(qtest_readb(qts, ram_offs), ==, 0xff); in test_tseg_size()
185 #define SMBASE 0x30000
[all …]
/qemu/hw/pci-host/
H A Dastro.c95 case 0x0008: in elroy_chip_read_with_attrs()
96 val = 0x6000005; /* func_class */ in elroy_chip_read_with_attrs()
98 case 0x0058: in elroy_chip_read_with_attrs()
107 case 0x0080: in elroy_chip_read_with_attrs()
110 case 0x0108: in elroy_chip_read_with_attrs()
113 case 0x200 ... 0x250 - 1: /* LMMIO, GMMIO, WLMMIO, WGMMIO, ... */ in elroy_chip_read_with_attrs()
114 index = (addr - 0x200) / 8; in elroy_chip_read_with_attrs()
117 case 0x0680: in elroy_chip_read_with_attrs()
120 case 0x0688: in elroy_chip_read_with_attrs()
121 val = 0; /* ERROR_STATUS */ in elroy_chip_read_with_attrs()
[all …]
/qemu/net/
H A Dl2tpv3.c50 /* Header set to 0x30000 signifies a data packet */
52 #define L2TPV3_DATA_PACKET 0x30000
57 #define IPPROTO_L2TP 0x73
209 *counter = 0; in l2tpv3_form_header()
241 message.msg_controllen = 0; in net_l2tpv3_receive_dgram_iov()
242 message.msg_flags = 0; in net_l2tpv3_receive_dgram_iov()
243 ret = RETRY_ON_EINTR(sendmsg(s->fd, &message, 0)); in net_l2tpv3_receive_dgram_iov()
244 if (ret > 0) { in net_l2tpv3_receive_dgram_iov()
246 } else if (ret == 0) { in net_l2tpv3_receive_dgram_iov()
248 * we should get an error and never a 0 send in net_l2tpv3_receive_dgram_iov()
[all …]
/qemu/hw/arm/
H A Dstm32f405_soc.c33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
[all …]
/qemu/target/xtensa/
H A Dcpu.h112 LBEG = 0,
171 #define PS_INTLEVEL 0xf
172 #define PS_INTLEVEL_SHIFT 0
174 #define PS_EXCM 0x10
175 #define PS_UM 0x20
177 #define PS_RING 0xc0
180 #define PS_OWB 0xf00
184 #define PS_CALLINC 0x30000
188 #define PS_WOE 0x40000
190 #define DEBUGCAUSE_IC 0x1
[all …]
/qemu/docs/system/i386/
H A Damd-memory-encryption.rst55 sev-guest,id=sev0,policy=0x1...\
61 sev-guest,id=sev0,policy=0x5...\
108 -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=1,policy=0x5
133 HMAC(0x04 || API_MAJOR || API_MINOR || BUILD || GCTX.POLICY || GCTX.LD || MNONCE; GCTX.TIK)
156 * if SEV-ES is enabled (``policy & 0x4 != 0``), ``vmsas_blob`` is the
187 | policy | hex | 0x30000 | a 64-bit guest policy |
189 | guest-visible-workarounds | string| 0 | 16-byte base64 encoded string|
217 | author-key-enabled | bool | 0 | auth block contains author key |
/qemu/hw/display/
H A Dati.c33 #define ATI_DEBUG_HW_CURSOR 0
38 #define DEFAULT_X_PIXMAN 0
61 uint32_t offs = s->regs.crtc_offset & 0x07ffffff; in ati_vga_switch_mode()
62 int stride = (s->regs.crtc_pitch & 0x7ff) * 8; in ati_vga_switch_mode()
63 int bpp = 0; in ati_vga_switch_mode()
66 if (s->regs.crtc_h_total_disp == 0) { in ati_vga_switch_mode()
69 if (s->regs.crtc_v_total_disp == 0) { in ati_vga_switch_mode()
98 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); in ati_vga_switch_mode()
99 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); in ati_vga_switch_mode()
108 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); in ati_vga_switch_mode()
[all …]
/qemu/qapi/
H A Dqom.json111 # "arguments": { "path": "/machine/unattached/device[0]",
478 # (default: "0")
481 # (default: "0")
528 # engine, 0 means that the engine will use its default.
529 # (default: 0)
532 # pool (default:0)
550 # events. 0 means polling is disabled (default: 32768 on POSIX
551 # hosts, 0 otherwise)
555 # long enough. 0 selects a default behaviour (default: 0)
559 # encountering events. 0 selects a default behaviour (default: 0)
[all …]
/qemu/hw/ide/
H A Datapi.c42 for(i = 0; i < buf_size; i++) { in padstr8()
53 buf[0] = (lba / 75) / 60; in lba_to_msf()
60 return !s->tray_open && s->nb_sectors > 0; in media_present()
77 buf[0] = 0x00; in cd_data_to_raw()
78 memset(buf + 1, 0xff, 10); in cd_data_to_raw()
79 buf[11] = 0x00; in cd_data_to_raw()
83 buf[3] = 0x01; /* mode 1 data */ in cd_data_to_raw()
88 memset(buf, 0, 288); in cd_data_to_raw()
103 ATAPI_SECTOR_SIZE, s->io_buffer, 0); in cd_read_sector_sync()
107 ATAPI_SECTOR_SIZE, s->io_buffer + 16, 0); in cd_read_sector_sync()
[all …]
/qemu/target/i386/
H A Dsev.c76 QEMU_BUILD_BUG_ON(sizeof(PaddedSevHashTable) % 16 != 0);
169 #define DEFAULT_GUEST_POLICY 0x1 /* disable debug */
171 #define DEFAULT_SEV_SNP_POLICY 0x30000
216 #define SNP_CPUID_FUNCTION_UNKNOWN 0xFFFFFFFF
243 memset(&input, 0x0, sizeof(input)); in sev_ioctl()
277 if (code < 0 || code >= SEV_FW_MAX_ERROR) { in fw_error_to_str()
396 return sev_common ? sev_common->cbitpos : 0; in sev_get_cbit_position()
404 return sev_common ? sev_common->reduced_phys_bits : 0; in sev_get_reduced_phys_bits()
495 if (r < 0) { in sev_get_pdh_info()
510 if (r < 0) { in sev_get_pdh_info()
[all …]

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