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/src/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8-gicv3.dtsi13 ranges = <0x0 0x0 0x2f000000 0x100000>;
15 reg = <0x0 0x2f000000 0x0 0x10000>,
16 <0x0 0x2f100000 0x0 0x200000>,
17 <0x0 0x2c000000 0x0 0x2000>,
18 <0x0 0x2c010000 0x0 0x2000>,
19 <0x0 0x2c02f000 0x0 0x2000>;
26 reg = <0x20000 0x20000>;
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
50 CPU_SLEEP_0: cpu-sleep-0 {
53 arm,psci-suspend-param = <0x0010000>;
60 CLUSTER_SLEEP_0: cluster-sleep-0 {
63 arm,psci-suspend-param = <0x1010000>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x000>;
76 i-cache-size = <0x8000>;
79 d-cache-size = <0x8000>;
[all …]
/src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic-v5-iwb.yaml35 const: 0
42 bits[3:0] trigger type and level flags.
69 reg = <0x2f000000 0x10000>;
71 #address-cells = <0>;
H A Darm,gic-v3.yaml33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
99 multipleOf: 0x10000
100 exclusiveMinimum: 0
[all …]
/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Predicates = [HasExtLBT] in {
19 def MOVGR2SCR : FmtGR2SCR<0x00000800>;
20 def MOVSCR2GR : FmtSCR2GR<0x00000c00>;
22 def JISCR0 : FmtJISCR<0x48000200>;
23 def JISCR1 : FmtJISCR<0x48000300>;
25 def ADDU12I_W : ALU_2RI5<0x00290000, simm5>;
27 def ADC_B : ALU_3R<0x00300000>;
28 def ADC_H : ALU_3R<0x00308000>;
29 def ADC_W : ALU_3R<0x00310000>;
[all …]
/src/usr.sbin/bhyve/riscv/
H A Dbhyverun_machdep.c64 #define UART_MMIO_BASE 0x10000
65 #define UART_MMIO_SIZE 0x1000
68 #define APLIC_MEM_BASE 0x2f000000
69 #define APLIC_MEM_SIZE 0x10000
127 if (bhyve_topology_parse(optarg) != 0) { in bhyve_optparse()
155 if (bhyve_pincpu_parse(optarg) != 0) { in bhyve_optparse()
162 if (strncmp(optarg, "help", strlen(optarg)) == 0) { in bhyve_optparse()
164 exit(0); in bhyve_optparse()
165 } else if (pci_parse_slot(optarg) != 0) in bhyve_optparse()
179 bhyve_usage(0); in bhyve_optparse()
[all …]
/src/usr.sbin/bhyve/aarch64/
H A Dbhyverun_machdep.c58 #define FDT_BASE 0x100000
62 #define UART_MMIO_BASE 0x10000
63 #define UART_MMIO_SIZE 0x1000
65 #define RTC_MMIO_BASE 0x11000
66 #define RTC_MMIO_SIZE 0x1000
69 #define GIC_DIST_BASE 0x2f000000
70 #define GIC_DIST_SIZE 0x10000
71 #define GIC_REDIST_BASE 0x2f100000
133 if (bhyve_topology_parse(optarg) != 0) { in bhyve_optparse()
164 if (bhyve_pincpu_parse(optarg) != 0) { in bhyve_optparse()
[all …]
/src/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h50 0x00000001, 0x00000002, 0x00000004, 0x00000008,
51 0x00000010, 0x00000020, 0x00000040, 0x00000080,
52 0x0000001b, 0x00000036
58 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
59 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
60 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
61 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
62 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
63 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
64 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/src/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]