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/linux-6.15/arch/arm/boot/dts/st/
Dstih407-pinctrl.dtsi11 /* 0-5: PIO_SBC */
50 reg = <0x0961f080 0x4>;
54 ranges = <0 0x09610000 0x6000>;
61 reg = <0x0 0x100>;
69 reg = <0x1000 0x100>;
77 reg = <0x2000 0x100>;
85 reg = <0x3000 0x100>;
93 reg = <0x4000 0x100>;
102 reg = <0x5000 0x100>;
104 st,retime-pin-mask = <0x3f>;
[all …]
Dste-nomadik-stn8815.dtsi14 reg = <0x00000000 0x04000000>,
15 <0x08000000 0x04000000>;
20 reg = <0x10210000 0x1000>;
37 reg = <0x101e2000 0x1000>;
46 reg = <0x101e3000 0x1000>;
55 reg = <0x101e4000 0x80>;
62 gpio-bank = <0>;
63 gpio-ranges = <&pinctrl 0 0 32>;
69 reg = <0x101e5000 0x80>;
77 gpio-ranges = <&pinctrl 0 32 32>;
[all …]
/linux-6.15/drivers/scsi/lpfc/
Dlpfc_sli.h102 #define LPFC_IO_FABRIC 0x10 /* Iocb send using fabric scheduler */
103 #define LPFC_DELAY_MEM_FREE 0x20 /* Defer free'ing of FC data */
104 #define LPFC_EXCHANGE_BUSY 0x40 /* SLI4 hba reported XB in response */
105 #define LPFC_USE_FCPWQIDX 0x80 /* Submit to specified FCPWQ index */
106 #define DSS_SECURITY_OP 0x100 /* security IO */
107 #define LPFC_IO_ON_TXCMPLQ 0x200 /* The IO is still on the TXCMPLQ */
108 #define LPFC_IO_DIF_PASS 0x400 /* T10 DIF IO pass-thru prot */
109 #define LPFC_IO_DIF_STRIP 0x800 /* T10 DIF IO strip prot */
110 #define LPFC_IO_DIF_INSERT 0x1000 /* T10 DIF IO insert prot */
111 #define LPFC_IO_CMD_OUTSTANDING 0x2000 /* timeout handler abort window */
[all …]
/linux-6.15/arch/sparc/mm/
Dfault_64.c87 u32 insn = 0; in get_user_insn()
112 __asm__ __volatile__("lduwa [%1] %2, %0" in get_user_insn()
127 __asm__ __volatile__("lduwa [%1] %2, %0" in get_user_insn()
174 addr = compute_effective_address(regs, insn, 0); in do_fault_siginfo()
188 if (!regs->tpc || (regs->tpc & 0x3)) in get_fault_insn()
189 return 0; in get_fault_insn()
214 (insn & 0xc0800000) == 0xc0800000) { in do_kernel_fault()
215 if (insn & 0x2000) in do_kernel_fault()
219 if ((asi & 0xf2) == 0x82) { in do_kernel_fault()
220 if (insn & 0x1000000) { in do_kernel_fault()
[all …]
/linux-6.15/arch/arm64/boot/dts/arm/
Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
16 ranges = <0 0x0 0x2a820000 0x20000>;
21 reg = <0x10000 0x10000>;
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
38 reg = <0x0 0x2b400000 0x0 0x10000>;
50 reg = <0x0 0x2b500000 0x0 0x10000>;
61 reg = <0x0 0x2b600000 0x0 0x10000>;
67 power-domains = <&scpi_devpd 0>;
72 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000>,
[all …]
/linux-6.15/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10.dtsi15 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
35 interrupts = <0 124 4>, <0 125 4>;
37 reg = <0xff111000 0x1000>,
38 <0xff113000 0x1000>;
45 reg = <0xffffd000 0x1000>,
46 <0xffffc100 0x100>;
65 reg = <0xffda1000 0x1000>;
66 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux-6.15/drivers/net/ethernet/freescale/
Dfec.h35 #define FEC_IEVENT 0x004 /* Interrupt event reg */
36 #define FEC_IMASK 0x008 /* Interrupt mask reg */
37 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
38 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
39 #define FEC_ECNTRL 0x024 /* Ethernet control reg */
40 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
41 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
42 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
43 #define FEC_R_CNTRL 0x084 /* Receive control reg */
44 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
[all …]
/linux-6.15/drivers/net/wireless/ti/wl1251/
Dreg.h14 #define REGISTERS_BASE 0x00300000
15 #define DRPW_BASE 0x00310000
17 #define REGISTERS_DOWN_SIZE 0x00008800
18 #define REGISTERS_WORK_SIZE 0x0000b000
20 #define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
23 #define ELPCTRL_WAKE_UP 0x1
24 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
25 #define ELPCTRL_SLEEP 0x0
27 #define ELPCTRL_WLAN_READY 0x2
30 #define SOR_CFG (REGISTERS_BASE + 0x0800)
[all …]
/linux-6.15/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c153 *value = ~0ULL; in etnaviv_gpu_get_param()
173 return 0; in etnaviv_gpu_get_param()
196 return 0; in etnaviv_gpu_reset_deassert()
215 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
220 gpu->identity.stream_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
222 gpu->identity.register_max = etnaviv_field(specs[0], in etnaviv_hw_specs()
224 gpu->identity.thread_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
226 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], in etnaviv_hw_specs()
228 gpu->identity.shader_core_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
230 gpu->identity.pixel_pipes = etnaviv_field(specs[0], in etnaviv_hw_specs()
[all …]
/linux-6.15/drivers/gpu/drm/xe/
Dxe_vm_doc.h56 * bind BO0 0x0-0x1000
57 * alloc page level 3a, program PTE[0] to BO0 phys address (CPU)
58 * alloc page level 2, program PDE[0] page level 3a phys address (CPU)
59 * alloc page level 1, program PDE[0] page level 2 phys address (CPU)
60 * update root PDE[0] to page level 1 phys address (GPU)
62 * bind BO1 0x201000-0x202000
66 * bind BO2 0x1ff000-0x201000
68 * update page level 3b PTE[0] to BO2 phys address + 0x1000 (GPU)
157 * 0x0000-0x2000 and 0x3000-0x5000 have mappings
158 * Munmap 0x1000-0x4000, results in mappings 0x0000-0x1000 and 0x4000-0x5000
[all …]
/linux-6.15/arch/arm64/boot/dts/exynos/
Dexynosautov9.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0>;
91 reg = <0x100>;
98 reg = <0x200>;
105 reg = <0x300>;
112 reg = <0x10000>;
119 reg = <0x10100>;
126 reg = <0x10200>;
133 reg = <0x10300>;
[all …]
/linux-6.15/include/linux/mfd/
Dlochnagar2_regs.h15 #define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D
16 #define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E
17 #define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F
18 #define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010
19 #define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011
20 #define LOCHNAGAR2_PSIA1_CTRL 0x0012
21 #define LOCHNAGAR2_PSIA2_CTRL 0x0013
22 #define LOCHNAGAR2_GF_AIF3_CTRL 0x0014
23 #define LOCHNAGAR2_GF_AIF4_CTRL 0x0015
24 #define LOCHNAGAR2_GF_AIF1_CTRL 0x0016
[all …]
/linux-6.15/arch/powerpc/boot/dts/fsl/
Dt208xrdb.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
Dt1023rdb.dts50 size = <0 0x1000000>;
51 alignment = <0 0x1000000>;
55 size = <0 0x400000>;
56 alignment = <0 0x400000>;
60 size = <0 0x2000000>;
61 alignment = <0 0x2000000>;
66 reg = <0xf 0xfe124000 0 0x2000>;
67 ranges = <0 0 0xf 0xe8000000 0x08000000
68 1 0 0xf 0xff800000 0x00010000>;
70 nor@0,0 {
[all …]
Dgef_sbc310.dts25 reg = <0x0 0x40000000>; // set by uboot
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00010000>; // FPGA
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
38 flash@0,0 {
40 reg = <0x0 0x0 0x01000000>;
[all …]
Dbsc9132si-post.dtsi40 interrupts = <16 2 0 0 20 2 0 0>;
43 /* controller at 0xa000 */
49 bus-range = <0 255>;
50 interrupts = <16 2 0 0>;
52 pcie@0 {
53 reg = <0 0 0 0 0>;
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
62 /* IDSEL 0x0 */
63 0000 0x0 0x0 0x1 &mpic 0x0 0x2 0x0 0x0
[all …]
Dc293pcie.dts46 reg = <0xf 0xffe1e000 0 0x2000>;
47 ranges = <0x0 0x0 0xf 0xec000000 0x04000000
48 0x1 0x0 0xf 0xff800000 0x00010000
49 0x2 0x0 0xf 0xffdf0000 0x00010000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 reg = <0xf 0xffe0a000 0 0x1000>;
59 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0x80000000
[all …]
/linux-6.15/drivers/dma/ioat/
Dregisters.h8 #define IOAT_PCI_DMACTRL_OFFSET 0x48
9 #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
10 #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
12 #define IOAT_PCI_DEVICE_ID_OFFSET 0x02
13 #define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148
14 #define IOAT_PCI_CHANERR_INT_OFFSET 0x180
15 #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184
18 #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
20 #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
25 #define IOAT_XFERCAP_32GB 0
[all …]
/linux-6.15/drivers/net/wireless/ath/ath9k/
Dreg_mci.h20 #define AR_MCI_COMMAND0 0x1800
21 #define AR_MCI_COMMAND0_HEADER 0xFF
22 #define AR_MCI_COMMAND0_HEADER_S 0
23 #define AR_MCI_COMMAND0_LEN 0x1f00
25 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000
28 #define AR_MCI_COMMAND1 0x1804
30 #define AR_MCI_COMMAND2 0x1808
31 #define AR_MCI_COMMAND2_RESET_TX 0x01
32 #define AR_MCI_COMMAND2_RESET_TX_S 0
33 #define AR_MCI_COMMAND2_RESET_RX 0x02
[all …]
/linux-6.15/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dpmmu_hbw_stlb_masks.h24 #define PMMU_HBW_STLB_BUSY_BUSY_SHIFT 0
25 #define PMMU_HBW_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define PMMU_HBW_STLB_ASID_ASID_SHIFT 0
29 #define PMMU_HBW_STLB_ASID_ASID_MASK 0x3FF
32 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
Ddcore0_hmmu0_stlb_masks.h24 #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0
25 #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0
29 #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF
32 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
Drot0_masks.h24 #define ROT0_KMD_MODE_EN_SHIFT 0
25 #define ROT0_KMD_MODE_EN_MASK 0x1
28 #define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0
29 #define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1
32 #define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0
33 #define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF
36 #define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0
37 #define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF
40 #define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0
41 #define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF
[all …]
Dpsoc_etr_masks.h24 #define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0
25 #define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF
28 #define PSOC_ETR_STS_FULL_SHIFT 0
29 #define PSOC_ETR_STS_FULL_MASK 0x1
31 #define PSOC_ETR_STS_TRIGGERED_MASK 0x2
33 #define PSOC_ETR_STS_TMCREADY_MASK 0x4
35 #define PSOC_ETR_STS_FTEMPTY_MASK 0x8
37 #define PSOC_ETR_STS_EMPTY_MASK 0x10
39 #define PSOC_ETR_STS_MEMERR_MASK 0x20
42 #define PSOC_ETR_RRD_RRD_SHIFT 0
[all …]
/linux-6.15/arch/powerpc/boot/dts/
Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux-6.15/drivers/usb/storage/
Dunusual_uas.h32 UNUSUAL_DEV(0x054c, 0x087d, 0x0000, 0x9999,
42 UNUSUAL_DEV(0x059f, 0x105f, 0x0000, 0x9999,
49 UNUSUAL_DEV(0x059f, 0x1061, 0x0000, 0x9999,
56 UNUSUAL_DEV(0x090c, 0x2000, 0x0000, 0x9999,
66 UNUSUAL_DEV(0x0984, 0x0301, 0x0128, 0x0128,
73 UNUSUAL_DEV(0x0b05, 0x1932, 0x0000, 0x9999,
80 UNUSUAL_DEV(0x0bc2, 0x331a, 0x0000, 0x9999,
87 UNUSUAL_DEV(0x125f, 0xa94a, 0x0160, 0x0160,
94 UNUSUAL_DEV(0x13fd, 0x3940, 0x0000, 0x9999,
101 UNUSUAL_DEV(0x152d, 0x0539, 0x0000, 0x9999,
[all …]

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