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/linux-6.15/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt12 "fsl,pamu-v1.0". The second is "fsl,pamu".
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
19 is 0x5000.
56 For PAMU v1.0, this size is 0x1000.
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
96 reg = <0x20000 0x5000>;
97 ranges = <0 0x20000 0x5000>;
98 fsl,portid-mapping = <0xf80000>;
102 24 2 0 0
105 pamu0: pamu@0 {
[all …]
/linux-6.15/drivers/scsi/qedf/
Dqedf_dbg.h24 #define QEDF_LOG_DEFAULT 0x1 /* Set default logging mask */
25 #define QEDF_LOG_INFO 0x2 /*
29 #define QEDF_LOG_DISC 0x4 /* Init, discovery, rport */
30 #define QEDF_LOG_LL2 0x8 /* LL2, VLAN logs */
31 #define QEDF_LOG_CONN 0x10 /* Connection setup, cleanup */
32 #define QEDF_LOG_EVT 0x20 /* Events, link, mtu */
33 #define QEDF_LOG_TIMER 0x40 /* Timer events */
34 #define QEDF_LOG_MP_REQ 0x80 /* Middle Path (MP) logs */
35 #define QEDF_LOG_SCSI_TM 0x100 /* SCSI Aborts, Task Mgmt */
36 #define QEDF_LOG_UNSOL 0x200 /* unsolicited event logs */
[all …]
/linux-6.15/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,cpm1-scc-qmc.yaml60 const: 0
63 '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
71 minimum: 0
152 reg = <0xa60 0x20>,
153 <0x3f00 0xc0>,
154 <0x2000 0x1000>;
160 #size-cells = <0>;
169 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
170 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
178 fsl,tx-ts-mask = <0x00000000 0x00000055>;
[all …]
/linux-6.15/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-vi.yaml15 pattern: "^vi@[0-9a-f]+$"
83 port@0:
89 "^csi@[0-9a-f]+$":
125 #size-cells = <0>;
128 reg = <0x48>;
141 reg = <0x54080000 0x00040000>;
151 #size-cells = <0>;
152 port@0 {
153 reg = <0>;
169 #size-cells = <0>;
[all …]
/linux-6.15/include/linux/mfd/arizona/
Dpdata.h15 #define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
18 #define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
21 #define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
24 #define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
27 #define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
30 #define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
33 #define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
36 #define ARIZONA_GPN_FN_MASK 0x007F /* GPN_FN - [6:0] */
37 #define ARIZONA_GPN_FN_SHIFT 0 /* GPN_FN - [6:0] */
38 #define ARIZONA_GPN_FN_WIDTH 7 /* GPN_FN - [6:0] */
[all …]
/linux-6.15/fs/afs/
Dafs_vl.h62 YFS_SERVER_INDEX = 0,
68 YFS_ENDPOINT_IPV4 = 0,
84 #define AFS_VLF_RWEXISTS 0x1000 /* R/W volume exists */
85 #define AFS_VLF_ROEXISTS 0x2000 /* R/O volume exists */
86 #define AFS_VLF_BACKEXISTS 0x4000 /* backup volume exists */
94 #define AFS_VLSF_NEWREPSITE 0x0001 /* Ignore all 'non-new' servers */
95 #define AFS_VLSF_ROVOL 0x0002 /* this server holds a R/O instance of the volume */
96 #define AFS_VLSF_RWVOL 0x0004 /* this server holds a R/W instance of the volume */
97 #define AFS_VLSF_BACKVOL 0x0008 /* this server holds a backup instance of the volume */
98 #define AFS_VLSF_UUID 0x0010 /* This server is referred to by its UUID */
[all …]
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgv100.c47 nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd)); in gv100_chan_ramfc_write()
48 nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd)); in gv100_chan_ramfc_write()
49 nvkm_wo32(chan->inst, 0x010, 0x0000face); in gv100_chan_ramfc_write()
50 nvkm_wo32(chan->inst, 0x030, 0x7ffff902); in gv100_chan_ramfc_write()
51 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset)); in gv100_chan_ramfc_write()
52 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16)); in gv100_chan_ramfc_write()
53 nvkm_wo32(chan->inst, 0x084, 0x20400000); in gv100_chan_ramfc_write()
54 nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm); in gv100_chan_ramfc_write()
55 nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000); in gv100_chan_ramfc_write()
56 nvkm_wo32(chan->inst, 0x0e8, chan->id); in gv100_chan_ramfc_write()
[all …]
/linux-6.15/drivers/net/hippi/
Drrunner.h172 #define RR_INT 0x01
173 #define RR_CLEAR_INT 0x02
174 #define NO_SWAP 0x04000004
175 #define NO_SWAP1 0x00000004
176 #define PCI_RESET_NIC 0x08
177 #define HALT_NIC 0x10
178 #define SSTEP_NIC 0x20
179 #define MEM_READ_MULTI 0x40
180 #define NIC_HALTED 0x100
181 #define HALT_INST 0x200
[all …]
/linux-6.15/arch/arm64/boot/dts/marvell/
Darmada-37xx.dtsi33 reg = <0 0x4000000 0 0x200000>;
38 reg = <0 0x4400000 0 0x1000000>;
45 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
83 /* 32M internal register @ 0xd000_0000 */
84 ranges = <0x0 0x0 0xd0000000 0x2000000>;
88 reg = <0x8300 0x40>;
96 reg = <0xd000 0x1000>;
102 #size-cells = <0>;
[all …]
/linux-6.15/arch/arm/boot/dts/mediatek/
Dmt7629.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
[all …]
Dmt7623.dtsi73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
[all …]
/linux-6.15/drivers/net/ethernet/ibm/emac/
Dphy.c69 if (val >= 0 && (val & BMCR_RESET) == 0) in emac_mii_reset_phy()
73 if ((val & BMCR_ISOLATE) && limit > 0) in emac_mii_reset_phy()
76 return limit <= 0; in emac_mii_reset_phy()
93 if (val >= 0 && (val & BMCR_RESET) == 0) in emac_mii_reset_gpcs()
97 if ((val & BMCR_ISOLATE) && limit > 0) in emac_mii_reset_gpcs()
100 if (limit > 0 && phy->mode == PHY_INTERFACE_MODE_SGMII) { in emac_mii_reset_gpcs()
102 gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */ in emac_mii_reset_gpcs()
103 gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */ in emac_mii_reset_gpcs()
104 gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX */ in emac_mii_reset_gpcs()
107 return limit <= 0; in emac_mii_reset_gpcs()
[all …]
/linux-6.15/arch/mips/kernel/
Dbmips_5xxx_init.S36 9: cache op, 0(t0) ; \
55 #define ICE_MASK 0x80000000
56 #define DCE_MASK 0x40000000
58 #define CP0_BRCM_CONFIG0 $22, 0
77 #define CP0_BRCM_MODE_BrHIST_MASK (0x1f << 20)
81 #define BRCM_ZSC_ALL_REGS_SELECT 0x7 << 24
83 #define BRCM_ZSC_CONFIG_REG 0 << 3
89 #define BRCM_ZSC_SCB0_ADDR_MAPPING_REG0 0xa << 3
90 #define BRCM_ZSC_SCB0_ADDR_MAPPING_REG1 0xc << 3
92 #define BRCM_ZSC_SCB1_ADDR_MAPPING_REG0 0xe << 3
[all …]
/linux-6.15/arch/powerpc/xmon/
Dppc.h92 #define PPC_OPCODE_COMMON 0x10
96 #define PPC_OPCODE_ANY 0x20
99 #define PPC_OPCODE_64 0x40
102 #define PPC_OPCODE_64_BRIDGE 0x80
105 #define PPC_OPCODE_ALTIVEC 0x100
108 #define PPC_OPCODE_403 0x200
111 #define PPC_OPCODE_BOOKE 0x400
114 #define PPC_OPCODE_440 0x800
117 #define PPC_OPCODE_POWER4 0x1000
120 #define PPC_OPCODE_POWER7 0x2000
[all …]
/linux-6.15/drivers/gpu/drm/amd/include/
Damd_shared.h38 AMD_ASIC_MASK = 0x0000ffffUL,
39 AMD_FLAGS_MASK = 0xffff0000UL,
40 AMD_IS_MOBILITY = 0x00010000UL,
41 AMD_IS_APU = 0x00020000UL,
42 AMD_IS_PX = 0x00040000UL,
43 AMD_EXP_HW_SUPPORT = 0x00080000UL,
47 AMD_APU_IS_RAVEN = 0x00000001UL,
48 AMD_APU_IS_RAVEN2 = 0x00000002UL,
49 AMD_APU_IS_PICASSO = 0x00000004UL,
50 AMD_APU_IS_RENOIR = 0x00000008UL,
[all …]
/linux-6.15/arch/arm64/boot/dts/hisilicon/
Dhi3670.dtsi25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
68 reg = <0x0 0x1>;
75 reg = <0x0 0x2>;
82 reg = <0x0 0x3>;
89 reg = <0x0 0x100>;
96 reg = <0x0 0x101>;
103 reg = <0x0 0x102>;
110 reg = <0x0 0x103>;
[all …]
/linux-6.15/drivers/net/phy/
Dmarvell-88q2xxx.c15 #define PHY_ID_88Q2220_REVB0 (MARVELL_PHY_ID_88Q2220 | 0x1)
16 #define PHY_ID_88Q2220_REVB1 (MARVELL_PHY_ID_88Q2220 | 0x2)
17 #define PHY_ID_88Q2220_REVB2 (MARVELL_PHY_ID_88Q2220 | 0x3)
20 #define MDIO_MMD_AN_MV_STAT_ANEG 0x0100
21 #define MDIO_MMD_AN_MV_STAT_LOCAL_RX 0x1000
22 #define MDIO_MMD_AN_MV_STAT_REMOTE_RX 0x2000
23 #define MDIO_MMD_AN_MV_STAT_LOCAL_MASTER 0x4000
24 #define MDIO_MMD_AN_MV_STAT_MS_CONF_FAULT 0x8000
27 #define MDIO_MMD_AN_MV_STAT2_AN_RESOLVED 0x0800
28 #define MDIO_MMD_AN_MV_STAT2_100BT1 0x2000
[all …]
/linux-6.15/drivers/gpu/drm/radeon/
Dpptable.h41 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
42 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected …
44 #define ATOM_PP_THERMALCONTROLLER_NONE 0
57 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented,…
58 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally
67 // We probably should reserve the bit 0x80 for this use.
71 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal…
72 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal…
135 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, …
136 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK durin…
[all …]
/linux-6.15/arch/mips/cavium-octeon/executive/
Dcvmx-helper-rgmii.c50 * Returns Number of RGMII/GMII/MII ports (0-4).
54 int num_ports = 0; in __cvmx_helper_rgmii_probe()
101 int index = port & 0xf; in cvmx_helper_rgmii_internal_loopback()
105 gmx_cfg.u64 = 0; in cvmx_helper_rgmii_internal_loopback()
110 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); in cvmx_helper_rgmii_internal_loopback()
111 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); in cvmx_helper_rgmii_internal_loopback()
127 * @port: Port to setup (0..3)
148 return 0; in __cvmx_helper_errata_asx_pass1()
155 * @interface: PKO Interface to configure (0 or 1)
170 if (mode.s.en == 0) in __cvmx_helper_rgmii_enable()
[all …]
/linux-6.15/arch/arm/boot/dts/rockchip/
Drv1126.dtsi36 #size-cells = <0>;
41 reg = <0xf00>;
49 reg = <0xf01>;
57 reg = <0xf02>;
65 reg = <0xf03>;
103 #clock-cells = <0>;
108 reg = <0xfe000000 0x20000>;
113 reg = <0xfe020000 0x1000>;
123 reg = <0xfe860000 0x20>;
128 reg = <0xfe860080 0x20>;
[all …]
/linux-6.15/arch/arm/boot/dts/allwinner/
Dsun8i-a23-a33.dtsi91 #size-cells = <0>;
93 cpu0: cpu@0 {
96 reg = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
136 reg = <0x01c00000 0x30>;
143 reg = <0x01d00000 0x80000>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
151 reg = <0x000000 0x80000>;
[all …]
/linux-6.15/drivers/scsi/
Ddc395x.h34 #if 0
38 #define NORM_REC_LVL 0
45 #define BIT31 0x80000000
46 #define BIT30 0x40000000
47 #define BIT29 0x20000000
48 #define BIT28 0x10000000
49 #define BIT27 0x08000000
50 #define BIT26 0x04000000
51 #define BIT25 0x02000000
52 #define BIT24 0x01000000
[all …]
/linux-6.15/arch/arm64/boot/dts/allwinner/
Dsun50i-h6.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
27 reg = <0>;
32 i-cache-size = <0x8000>;
35 d-cache-size = <0x8000>;
49 i-cache-size = <0x8000>;
52 d-cache-size = <0x8000>;
66 i-cache-size = <0x8000>;
69 d-cache-size = <0x8000>;
83 i-cache-size = <0x8000>;
[all …]
/linux-6.15/sound/core/seq/oss/
Dseq_oss_event.c37 * return 0 : enqueued
99 return note_off_event(dp, 0, q->n.chn, q->n.note, q->n.vel, ev); in old_event()
102 return note_on_event(dp, 0, q->n.chn, q->n.note, q->n.vel, ev); in old_event()
109 return set_control_event(dp, 0, SNDRV_SEQ_EVENT_PGMCHANGE, in old_event()
110 q->n.chn, 0, q->n.note, ev); in old_event()
134 q->e.chn, 0, q->e.p1, ev); in extended_event()
138 q->e.chn, 0, q->e.p1, ev); in extended_event()
141 /* convert -128:127 to 0:127 */ in extended_event()
151 /* -0x2000:0x1fff */ in extended_event()
154 q->e.chn, 0, val, ev); in extended_event()
[all …]
/linux-6.15/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]

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