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/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-a1.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
32 reg = <0x0 0x1>;
55 size = <0x0 0x800000>;
56 alignment = <0x0 0x400000>;
79 reg = <0x0 0xfe000000 0x0 0x1000000>;
82 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
85 reset: reset-controller@0 {
87 reg = <0x0 0x0 0x0 0x8c>;
[all …]
/linux-5.10/arch/arm/boot/dts/
Dexynos3250.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0>;
100 xusbxti: clock-0 {
102 clock-frequency = <0>;
103 #clock-cells = <0>;
109 clock-frequency = <0>;
110 #clock-cells = <0>;
116 clock-frequency = <0>;
117 #clock-cells = <0>;
[all …]
Dbcm7445.dtsi17 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
50 reg = <0x00 0xffd01000 0x00 0x1000>,
51 <0x00 0xffd02000 0x00 0x2000>,
52 <0x00 0xffd04000 0x00 0x2000>,
53 <0x00 0xffd06000 0x00 0x2000>;
70 ranges = <0 0x00 0xf0000000 0x1000000>;
74 reg = <0x40ab00 0x20>;
84 reg = <0x404000 0x51c>;
[all …]
Decx-2000.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
54 memory@0 {
57 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
63 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
67 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
70 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
71 <1 14 0xf08>,
[all …]
Daxm55xx.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 reg = <0x20 0x10020000 0 0x20000>;
58 #address-cells = <0>;
60 reg = <0x20 0x01001000 0 0x1000>,
61 <0x20 0x01002000 0 0x2000>,
62 <0x20 0x01004000 0 0x2000>,
63 <0x20 0x01006000 0 0x2000>;
97 reg = <0x20 0x10030000 0 0x2000>;
[all …]
Dmt6580.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
29 reg = <0x1>;
34 reg = <0x2>;
39 reg = <0x3>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10008000 0x80>;
[all …]
Dexynos5260.dtsi35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x0>;
47 reg = <0x1>;
54 reg = <0x100>;
61 reg = <0x101>;
68 reg = <0x102>;
75 reg = <0x103>;
88 reg = <0x10010000 0x10000>;
94 reg = <0x10200000 0x10000>;
[all …]
Dmstar-v7.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0>;
53 ranges = <0x16001000 0x16001000 0x00007000>,
54 <0x1f000000 0x1f000000 0x00400000>,
55 <0xa0000000 0xa0000000 0x20000>;
59 reg = <0x16001000 0x1000>,
60 <0x16002000 0x2000>,
61 <0x16004000 0x2000>,
62 <0x16006000 0x2000>;
[all …]
Dmt6589.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
29 reg = <0x1>;
34 reg = <0x2>;
39 reg = <0x3>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
77 reg = <0x10008000 0x80>;
[all …]
/linux-5.10/arch/arm64/boot/dts/synaptics/
Das370.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
37 reg = <0x1>;
46 reg = <0x2>;
55 reg = <0x3>;
67 CPU_SLEEP_0: cpu-sleep-0 {
70 arm,psci-suspend-param = <0x0010000>;
80 #clock-cells = <0>;
108 ranges = <0 0 0xf7000000 0x1000000>;
[all …]
/linux-5.10/include/uapi/linux/
Dmii.h16 #define MII_BMCR 0x00 /* Basic mode control register */
17 #define MII_BMSR 0x01 /* Basic mode status register */
18 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
19 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
20 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
21 #define MII_LPA 0x05 /* Link partner ability reg */
22 #define MII_EXPANSION 0x06 /* Expansion register */
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
25 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux-5.10/drivers/net/ethernet/amd/
Dam79c961a.h9 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
15 #define NET_DEBUG 0
18 #define NET_UID 0
19 #define NET_RDP 0x10
20 #define NET_RAP 0x12
21 #define NET_RESET 0x14
22 #define NET_IDP 0x16
27 #define CSR0 0
28 #define CSR0_INIT 0x0001
29 #define CSR0_STRT 0x0002
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/socionext/
Dsocionext,uniphier-system-cache.yaml70 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
71 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
73 cache-size = <0x140000>;
83 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
84 interrupts = <0 190 4>, <0 191 4>;
86 cache-size = <0x200000>;
95 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
96 interrupts = <0 174 4>, <0 175 4>;
98 cache-size = <0x200000>;
/linux-5.10/drivers/gpu/drm/msm/adreno/
Da2xx_gpu.c19 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
43 OUT_RING(ring, 0x00000000); in a2xx_submit()
50 OUT_RING(ring, 0x80000000); in a2xx_submit()
57 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
61 /* All fields present (bits 9:0) */ in a2xx_me_init()
62 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
64 OUT_RING(ring, 0x00000000); in a2xx_me_init()
66 OUT_RING(ring, 0x00000000); in a2xx_me_init()
68 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dheadnv04.c30 nvkm_wr32(device, 0x600140 + (head->id * 0x2000) , 0x00000000); in nv04_head_vblank_put()
37 nvkm_wr32(device, 0x600140 + (head->id * 0x2000) , 0x00000001); in nv04_head_vblank_get()
44 u32 data = nvkm_rd32(device, 0x600868 + (head->id * 0x2000)); in nv04_head_rgpos()
45 *hline = (data & 0xffff0000) >> 16; in nv04_head_rgpos()
46 *vline = (data & 0x0000ffff); in nv04_head_rgpos()
53 const u32 hoff = head->id * 0x0200; in nv04_head_state()
54 state->vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0x0000ffff; in nv04_head_state()
55 state->vtotal = nvkm_rd32(device, 0x680804 + hoff) & 0x0000ffff; in nv04_head_state()
57 state->hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0x0000ffff; in nv04_head_state()
58 state->htotal = nvkm_rd32(device, 0x680824 + hoff) & 0x0000ffff; in nv04_head_state()
Dvga.c30 return nvkm_rd08(device, 0x601000 + port); in nvkm_rdport()
32 if (port == 0x03c0 || port == 0x03c1 || /* AR */ in nvkm_rdport()
33 port == 0x03c2 || port == 0x03da || /* INP0 */ in nvkm_rdport()
34 port == 0x03d4 || port == 0x03d5) /* CR */ in nvkm_rdport()
35 return nvkm_rd08(device, 0x601000 + (head * 0x2000) + port); in nvkm_rdport()
37 if (port == 0x03c2 || port == 0x03cc || /* MISC */ in nvkm_rdport()
38 port == 0x03c4 || port == 0x03c5 || /* SR */ in nvkm_rdport()
39 port == 0x03ce || port == 0x03cf) { /* GR */ in nvkm_rdport()
41 head = 0; /* CR44 selects head */ in nvkm_rdport()
42 return nvkm_rd08(device, 0x0c0000 + (head * 0x2000) + port); in nvkm_rdport()
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgk104.c58 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); in gk104_fifo_engine_status()
60 status->busy = !!(stat & 0x80000000); in gk104_fifo_engine_status()
61 status->faulted = !!(stat & 0x40000000); in gk104_fifo_engine_status()
62 status->next.tsg = !!(stat & 0x10000000); in gk104_fifo_engine_status()
63 status->next.id = (stat & 0x0fff0000) >> 16; in gk104_fifo_engine_status()
64 status->chsw = !!(stat & 0x00008000); in gk104_fifo_engine_status()
65 status->save = !!(stat & 0x00004000); in gk104_fifo_engine_status()
66 status->load = !!(stat & 0x00002000); in gk104_fifo_engine_status()
67 status->prev.tsg = !!(stat & 0x00001000); in gk104_fifo_engine_status()
68 status->prev.id = (stat & 0x00000fff); in gk104_fifo_engine_status()
[all …]
/linux-5.10/arch/powerpc/boot/dts/
Dmpc7448hpc2.dts29 #size-cells =<0>;
31 PowerPC,7448@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 clock-frequency = <0>; // From U-Boot
40 bus-frequency = <0>; // From U-Boot
46 reg = <0x0 0x20000000 // DDR2 512M at 0
54 ranges = <0x0 0xc0000000 0x10000>;
[all …]
/linux-5.10/arch/arm/mach-ux500/
Ddb8500-regs.h10 #define U8500_ESRAM_BASE 0x40000000
11 #define U8500_ESRAM_BANK_SIZE 0x00020000
21 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
28 #define U8500_PER3_BASE 0x80000000
29 #define U8500_STM_BASE 0x80100000
30 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
31 #define U8500_PER2_BASE 0x80110000
32 #define U8500_PER1_BASE 0x80120000
33 #define U8500_B2R2_BASE 0x80130000
34 #define U8500_HSEM_BASE 0x80140000
[all …]
/linux-5.10/drivers/gpu/drm/amd/display/dc/basics/
Ddc_common.c87 && plane_state->coeff_reduction_factor.value != 0) { in build_prescale_params()
96 bias_and_scale->scale_blue = 0x2000; in build_prescale_params()
97 bias_and_scale->scale_red = 0x2000; in build_prescale_params()
98 bias_and_scale->scale_green = 0x2000; in build_prescale_params()
/linux-5.10/arch/powerpc/platforms/52xx/
Dmpc52xx_sleep.S14 ori r7, r7, 0x8000 /* EE */
18 li r10, 0 /* flag that irq handler sets */
21 lwz r8, 0x14(r6) /* intr->main_mask */
22 ori r8, r8, 0x1
23 xori r8, r8, 0x1
24 stw r8, 0x14(r6)
28 li r8, 0x1
29 stw r8, 0x40(r6) /* intr->main_emulate */
39 ori r10, r10, 0x2000
55 ori r10, r10, 0x2000
[all …]
/linux-5.10/arch/arc/boot/dts/
Dvdk_axs10x_mb.dtsi13 ranges = <0x00000000 0xe0000000 0x10000000>;
20 #clock-cells = <0>;
26 #clock-cells = <0>;
30 #clock-cells = <0>;
39 reg = < 0x18000 0x2000 >;
43 snps,phy-addr = < 0 >; // VDK model phy address is 0
51 reg = < 0x40000 0x100 >;
57 reg = <0x20000 0x100>;
67 reg = <0x21000 0x100>;
77 reg = <0x22000 0x100>;
[all …]

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