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/linux-6.8/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
Dgm107.c33 nvkm_wr32(device, 0x17e270, start); in gm107_ltc_cbc_clear()
34 nvkm_wr32(device, 0x17e274, limit); in gm107_ltc_cbc_clear()
35 nvkm_mask(device, 0x17e26c, 0x00000000, 0x00000004); in gm107_ltc_cbc_clear()
43 for (c = 0; c < ltc->ltc_nr; c++) { in gm107_ltc_cbc_wait()
44 for (s = 0; s < ltc->lts_nr; s++) { in gm107_ltc_cbc_wait()
45 const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200); in gm107_ltc_cbc_wait()
47 0x00000004, 0x00000000); in gm107_ltc_cbc_wait()
56 nvkm_mask(device, 0x17e338, 0x0000000f, i); in gm107_ltc_zbc_clear_color()
57 nvkm_wr32(device, 0x17e33c, color[0]); in gm107_ltc_zbc_clear_color()
58 nvkm_wr32(device, 0x17e340, color[1]); in gm107_ltc_zbc_clear_color()
[all …]
/linux-6.8/Documentation/devicetree/bindings/pci/
Drockchip-dw-pcie.yaml104 const: 0
176 reg = <0x3 0xc0800000 0x0 0x390000>,
177 <0x0 0xfe280000 0x0 0x10000>,
178 <0x3 0x80000000 0x0 0x100000>;
180 bus-range = <0x20 0x2f>;
196 msi-map = <0x2000 &its 0x2000 0x1000>;
201 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
202 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
210 #address-cells = <0>;
/linux-6.8/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/linux-6.8/drivers/net/ethernet/sis/
Dsis900.h19 #define SIS900_TOTAL_SIZE 0x100
23 cr=0x0, //Command Register
24 cfg=0x4, //Configuration Register
25 mear=0x8, //EEPROM Access Register
26 ptscr=0xc, //PCI Test Control Register
27 isr=0x10, //Interrupt Status Register
28 imr=0x14, //Interrupt Mask Register
29 ier=0x18, //Interrupt Enable Register
30 epar=0x18, //Enhanced PHY Access Register
31 txdp=0x20, //Transmit Descriptor Pointer Register
[all …]
/linux-6.8/Documentation/devicetree/bindings/net/
Dcpsw.txt37 driven low so that cpsw slave 0 and phy data
73 reg = <0x4A100000 0x1000>;
74 interrupts = <55 0x4>;
78 bd_ram_size = <0x2000>;
80 mac_control = <0x20>;
82 active_slave = <0>;
83 cpts_clock_mult = <0x80000000>;
87 cpsw_emac0: slave@0 {
88 phy_id = <&davinci_mdio>, <0>;
92 phys = <&phy_gmii_sel 1 0>;
[all …]
/linux-6.8/Documentation/devicetree/bindings/soc/amlogic/
Damlogic,meson-gx-hhi-sysctrl.yaml99 reg = <0xc883c000 0x2000>;
102 ranges = <0x0 0xc883c000 0x2000>;
104 sysctrl: system-controller@0 {
106 reg = <0 0x400>;
143 reg = <0xc8100000 0x100000>;
146 ranges = <0x0 0xc8100000 0x100000>;
148 sysctrl_AO: system-controller@0 {
150 reg = <0 0x100>;
165 reg = <0xff63c000 0x400>;
191 #phy-cells = <0>;
/linux-6.8/arch/arm64/boot/dts/lg/
Dlg1313.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
[all …]
Dlg1312.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
[all …]
/linux-6.8/drivers/net/ethernet/i825xx/
Dsun3_82586.h23 #define IEOB_NORSET 0x80 /* don't reset the board */
24 #define IEOB_ONAIR 0x40 /* put us on the air */
25 #define IEOB_ATTEN 0x20 /* attention! */
26 #define IEOB_IENAB 0x10 /* interrupt enable */
27 #define IEOB_XXXXX 0x08 /* free bit */
28 #define IEOB_XCVRL2 0x04 /* level 2 transceiver? */
29 #define IEOB_BUSERR 0x02 /* bus error */
30 #define IEOB_INT 0x01 /* interrupt */
33 #define IE_OBIO 0xc0000
39 #define SCP_DEFAULT_ADDRESS 0xfffff4
[all …]
/linux-6.8/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dnic0_qm0_masks.h23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
/linux-6.8/Documentation/devicetree/bindings/interrupt-controller/
Dti,pruss-intc.yaml18 interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
37 pattern: "^interrupt-controller@[0-9a-f]+$"
66 pattern: host_intr[0-7]
88 Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
114 pruss: pruss@0 {
116 reg = <0x0 0x80000>;
123 reg = <0x20000 0x2000>;
138 pruss@0 {
140 reg = <0x0 0x40000>;
147 reg = <0x20000 0x2000>;
[all …]
/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_10_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/linux-6.8/drivers/scsi/
Dqlogicpti.h11 #define SBUS_CFG1 0x006UL
12 #define SBUS_CTRL 0x008UL
13 #define SBUS_STAT 0x00aUL
14 #define SBUS_SEMAPHORE 0x00cUL
15 #define CMD_DMA_CTRL 0x022UL
16 #define DATA_DMA_CTRL 0x042UL
17 #define MBOX0 0x080UL
18 #define MBOX1 0x082UL
19 #define MBOX2 0x084UL
20 #define MBOX3 0x086UL
[all …]
/linux-6.8/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dpdma0_qm_masks.h24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
Ddcore0_edma0_qm_masks.h24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
/linux-6.8/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm4908.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 cpu-release-addr = <0x0 0xfff8>;
40 reg = <0x1>;
42 cpu-release-addr = <0x0 0xfff8>;
49 reg = <0x2>;
51 cpu-release-addr = <0x0 0xfff8>;
58 reg = <0x3>;
60 cpu-release-addr = <0x0 0xfff8>;
[all …]
/linux-6.8/arch/arm/boot/dts/ti/omap/
Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/linux-6.8/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.h57 #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
58 #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
59 #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
60 #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
61 #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
62 #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
63 #define L2CB_V10 0xc0
64 #define L2CB_V11 0xc1
65 #define L2CB_V20 0xc0
66 #define L2CB_V21 0xc1
[all …]
/linux-6.8/arch/arm/boot/dts/ti/davinci/
Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/linux-6.8/arch/mips/generic/
Dboard-ingenic.c34 return "X2000"; in ingenic_get_system_type()
64 #define INGENIC_CGU_BASE 0x10000000
77 if (offset < 0) in ingenic_force_12M_ext()
94 cgu = ioremap(INGENIC_CGU_BASE, 0x4); in ingenic_force_12M_ext()
114 if (!fdt_node_check_compatible(fdt, 0, "qi,lb60") && in ingenic_fixup_fdt()
115 fdt_path_offset(fdt, "/memory") < 0) in ingenic_fixup_fdt()
116 early_init_dt_add_memory_arch(0, SZ_32M); in ingenic_fixup_fdt()
150 { .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000 },
181 return 0; in ingenic_pm_enter()
197 return 0; in ingenic_pm_init()
/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]

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