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/linux-6.8/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
Dphy_cmn.c33 /* modulo inc/dec - assumes x E [0, bound - 1] */
34 #define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
143 pi->phy_wreg = 0; in wlc_radioreg_exit()
144 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0); in wlc_radioreg_exit()
152 return 0xffff; in read_radio_reg()
183 pi->phy_wreg = 0; in read_radio_reg()
204 pi->phy_wreg = 0; in write_radio_reg()
215 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 0); in read_radio_id()
222 id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4) in read_radio_id()
223 & 0xf); in read_radio_id()
[all …]
/linux-6.8/drivers/misc/
Dxilinx_sdfec.c34 #define XSDFEC_CODE_WR_PROTECT_ADDR (0x4)
37 #define XSDFEC_ACTIVE_ADDR (0x8)
38 #define XSDFEC_IS_ACTIVITY_SET (0x1)
41 #define XSDFEC_AXIS_WIDTH_ADDR (0xC)
45 #define XSDFEC_AXIS_DIN_WIDTH_LSB (0)
48 #define XSDFEC_AXIS_ENABLE_ADDR (0x10)
49 #define XSDFEC_AXIS_OUT_ENABLE_MASK (0x38)
50 #define XSDFEC_AXIS_IN_ENABLE_MASK (0x7)
55 #define XSDFEC_FEC_CODE_ADDR (0x14)
58 #define XSDFEC_ORDER_ADDR (0x18)
[all …]
/linux-6.8/include/linux/mlx4/
Ddevice.h62 #define MLX4_RATELIMIT_DEFAULT 0x00ff
68 MLX4_FLAG_MSI_X = 1 << 0,
93 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
94 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
155 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
189 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
233 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
238 MLX4_VF_CAP_FLAG_RESET = 1 << 0
247 * This enum may use only bits 0..7.
255 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
[all …]
/linux-6.8/drivers/net/wireless/ath/ath12k/
Dwmi.h46 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */
51 #define HE_PET_0_USEC 0
60 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1)
61 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1)
62 #define WMI_TLV_CMD_UNSUPPORTED 0
63 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0
64 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0
75 #define WMI_TLV_LEN GENMASK(15, 0)
79 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
83 #define WMI_HOST_RC_DS_FLAG 0x01
[all …]
/linux-6.8/drivers/dma/ti/
Dcppi41.c18 #define DESC_TYPE_HOST 0x10
19 #define DESC_TYPE_TEARD 0x13
31 #define DMA_TXGCR(x) (0x800 + (x) * 0x20)
32 #define DMA_RXGCR(x) (0x808 + (x) * 0x20)
41 #define DMA_SCHED_CTRL 0
43 #define DMA_SCHED_WORD(x) ((x) * 4 + 0x800)
45 #define SCHED_ENTRY0_CHAN(x) ((x) << 0)
64 #define QMGR_LRAM0_BASE 0x80
65 #define QMGR_LRAM_SIZE 0x84
66 #define QMGR_LRAM1_BASE 0x88
[all …]
/linux-6.8/arch/powerpc/platforms/512x/
Dclock-commonclk.c220 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); in mpc512x_clk_fixed()
251 return clk_register_divider_table(NULL, name, parent_name, 0, in mpc512x_clk_divtable()
339 /* 0b000 is "times 36" */ in get_cpmf_mult_x2()
343 /* 0b000 is "bypass" */ in get_cpmf_mult_x2()
370 { .div = 0, },
379 { .div = 0, },
388 val = 0; in get_freq_from_dt()
403 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
526 MCLK_TYPE_PSC, 0, \
535 MCLK_TYPE_MSCAN, 0, \
[all …]
/linux-6.8/drivers/mmc/host/
Dtmio_mmc_core.c125 host->sg_off = 0; in tmio_mmc_init_sg()
131 host->sg_off = 0; in tmio_mmc_next_sg()
194 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000); in tmio_mmc_reset()
196 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); in tmio_mmc_reset()
215 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001); in tmio_mmc_reset()
276 #define APP_CMD 0x0040
277 #define RESP_NONE 0x0300
278 #define RESP_R1 0x0400
279 #define RESP_R1B 0x0500
280 #define RESP_R2 0x0600
[all …]
/linux-6.8/drivers/gpu/drm/amd/pm/swsmu/inc/
Damdgpu_smu.h35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
38 #define SMU_FW_NAME_LEN 0x24
40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
45 #define SMU_THROTTLER_PPT0_BIT 0
103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
[all …]
/linux-6.8/arch/x86/
DKconfig143 # Word-size accesses may read uninitialized data past the trailing \0
385 default 0xdffffc0000000000
1253 0xffffffffff600?00.
1357 major 202 and minors 0 to 31 for /dev/cpu/0/msr to /dev/cpu/31/msr.
1366 with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to
1462 default 0xB0000000 if VMSPLIT_3G_OPT
1463 default 0x80000000 if VMSPLIT_2G
1464 default 0x78000000 if VMSPLIT_2G_OPT
1465 default 0x40000000 if VMSPLIT_1G
1466 default 0xC0000000
[all …]
/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h26 #define ixCLIPPER_DEBUG_REG00 0x0000
27 #define ixCLIPPER_DEBUG_REG01 0x0001
28 #define ixCLIPPER_DEBUG_REG02 0x0002
29 #define ixCLIPPER_DEBUG_REG03 0x0003
30 #define ixCLIPPER_DEBUG_REG04 0x0004
31 #define ixCLIPPER_DEBUG_REG05 0x0005
32 #define ixCLIPPER_DEBUG_REG06 0x0006
33 #define ixCLIPPER_DEBUG_REG07 0x0007
34 #define ixCLIPPER_DEBUG_REG08 0x0008
35 #define ixCLIPPER_DEBUG_REG09 0x0009
[all …]
/linux-6.8/arch/powerpc/boot/dts/fsl/
Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux-6.8/arch/arm64/boot/dts/freescale/
Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
61 interrupts = <1 9 0x4>;
66 reg = <0x0 0x6020000 0 0x20000>;
[all …]
/linux-6.8/drivers/scsi/
Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux-6.8/include/linux/
Defi.h32 #define EFI_SUCCESS 0
57 #define __efiapi __attribute__((regparm(0)))
78 (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
79 (b) & 0xff, ((b) >> 8) & 0xff, \
80 (c) & 0xff, ((c) >> 8) & 0xff, d } }
98 #define EFI_RESERVED_TYPE 0
117 #define EFI_MEMORY_UC ((u64)0x0000000000000001ULL) /* uncached */
118 #define EFI_MEMORY_WC ((u64)0x0000000000000002ULL) /* write-coalescing */
119 #define EFI_MEMORY_WT ((u64)0x0000000000000004ULL) /* write-through */
120 #define EFI_MEMORY_WB ((u64)0x0000000000000008ULL) /* write-back */
[all …]
Dnvme.h28 #define NVME_NSID_ALL 0xffffffff
48 NVME_DCTYPE_NOT_REPORTED = 0,
55 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
75 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
112 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
128 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
129 NVME_REG_VS = 0x0008, /* Version */
130 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
131 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
132 NVME_REG_CC = 0x0014, /* Controller Configuration */
[all …]
/linux-6.8/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2.h28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
[all …]
/linux-6.8/arch/mips/include/asm/sibyte/
Dbcm1480_regs.h70 #define A_BCM1480_MC_BASE_0 0x0010050000
71 #define A_BCM1480_MC_BASE_1 0x0010051000
72 #define A_BCM1480_MC_BASE_2 0x0010052000
73 #define A_BCM1480_MC_BASE_3 0x0010053000
74 #define BCM1480_MC_REGISTER_SPACING 0x1000
79 #define R_BCM1480_MC_CONFIG 0x0000000100
80 #define R_BCM1480_MC_CS_START 0x0000000120
81 #define R_BCM1480_MC_CS_END 0x0000000140
84 #define R_BCM1480_MC_CS01_ROW0 0x0000000180
85 #define R_BCM1480_MC_CS01_ROW1 0x00000001A0
[all …]
/linux-6.8/arch/arm64/boot/dts/renesas/
Dr8a77970.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
60 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
69 clock-frequency = <0>;
87 #clock-cells = <0>;
[all …]
/linux-6.8/drivers/media/i2c/
Dar0521.c31 #define AR0521_MIN_X_ADDR_START 0u
32 #define AR0521_MIN_Y_ADDR_START 0u
46 #define AR0521_ANA_GAIN_MIN 0x00
47 #define AR0521_ANA_GAIN_MAX 0x3f
48 #define AR0521_ANA_GAIN_STEP 0x01
49 #define AR0521_ANA_GAIN_DEFAULT 0x00
52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300
53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340
55 #define AR0521_REG_CHIP_ID 0x3000
56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
[all …]
/linux-6.8/arch/x86/events/intel/
Duncore_snb.c7 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
8 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
9 #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150
10 #define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
11 #define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04
12 #define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604
13 #define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904
14 #define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c
15 #define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900
16 #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910
[all …]
/linux-6.8/drivers/net/wireless/microchip/wilc1000/
Dwlan_if.h22 WILC_FW_BSS_TYPE_INFRA = 0,
28 WILC_FW_OPER_MODE_B_ONLY = 0, /* 1, 2 M, otherwise 5, 11 M */
35 WILC_FW_PREAMBLE_SHORT = 0, /* Short Preamble */
41 WILC_FW_PASSIVE_SCAN = 0,
46 WILC_FW_NO_POWERSAVE = 0,
54 WILC_BUS_ACQUIRE_ONLY = 0,
59 WILC_BUS_RELEASE_ONLY = 0,
64 WILC_FW_NO_ENCRYPT = 0,
65 WILC_FW_ENCRYPT_ENABLED = BIT(0),
97 WILC_FW_MFP_NONE = 0x0,
[all …]
/linux-6.8/drivers/gpu/drm/amd/amdkfd/
Dcwsr_trap_handler_gfx10.asm50 var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006
51 var SQ_WAVE_STATUS_HALT_MASK = 0x2000
52 var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000
69 var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400
70 var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF
72 var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80
74 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100
76 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF
77 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0
79 var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800
[all …]
Dcwsr_trap_handler_gfx9.asm48 … = 1 //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger
55 var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006
56 var SQ_WAVE_STATUS_HALT_MASK = 0x2000
57 var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0
61 var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK = 0x400000
62 var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000
78 var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400
79 var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF
81 var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80
83 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100
[all …]
/linux-6.8/drivers/media/tuners/
Dxc5000.c29 MODULE_PARM_DESC(no_poweroff, "0 (default) powers device off when not used.\n"
72 #define XC_RF_MODE_AIR 0
76 #define XC_PRODUCT_ID_FW_NOT_LOADED 0x2000
77 #define XC_PRODUCT_ID_FW_LOADED 0x1388
80 #define XREG_INIT 0x00
81 #define XREG_VIDEO_MODE 0x01
82 #define XREG_AUDIO_MODE 0x02
83 #define XREG_RF_FREQ 0x03
84 #define XREG_D_CODE 0x04
85 #define XREG_IF_OUT 0x05
[all …]
/linux-6.8/drivers/scsi/aic94xx/
Daic94xx_sds.c30 u8 major; /* 0 */
31 u8 minor; /* 0 */
37 #define OCM_DE_OCM_DIR 0x00
38 #define OCM_DE_WIN_DRVR 0x01
39 #define OCM_DE_BIOS_CHIM 0x02
40 #define OCM_DE_RAID_ENGN 0x03
41 #define OCM_DE_BIOS_INTL 0x04
42 #define OCM_DE_BIOS_CHIM_OSM 0x05
43 #define OCM_DE_BIOS_CHIM_DYNAMIC 0x06
44 #define OCM_DE_ADDC2C_RES0 0x07
[all …]

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