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/linux-6.15/arch/arm64/boot/dts/qcom/
Dmsm8976.dtsi26 #clock-cells = <0>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
48 reg = <0x1>;
59 reg = <0x2>;
70 reg = <0x3>;
81 reg = <0x100>;
92 reg = <0x101>;
103 reg = <0x102>;
[all …]
Dsc7180-acer-aspire1.dts35 reg = <0x0 0x80840000 0 0x2000>;
40 reg = <0x0 0x85b00000 0 0x500000>;
45 reg = <0x0 0x86000000 0x0 0x2000000>;
50 reg = <0x0 0x8e400000 0x0 0x2800000>;
55 reg = <0x0 0x93900000 0x0 0x200000>;
64 pinctrl-0 = <&amp_sd_mode_default>;
67 #sound-dai-cells = <0>;
75 pinctrl-0 = <&soc_bkoff_default>;
88 pinctrl-0 = <&reg_edp_1p2_en_default>;
103 pinctrl-0 = <&reg_edp_1p8_en_default>;
[all …]
Dmsm8998-sony-xperia-yoshino.dtsi18 qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */
19 qcom,board-id = <8 0>;
24 pinctrl-0 = <&div_clk1>;
27 #clock-cells = <0>;
45 startup-delay-us = <0>;
49 pinctrl-0 = <&main_cam_pwr_en>;
55 startup-delay-us = <0>;
59 pinctrl-0 = <&chat_cam_pwr_en>;
66 startup-delay-us = <0>;
70 pinctrl-0 = <&main_cam_pwr_io_en>;
[all …]
Dsdm845.dtsi78 #clock-cells = <0>;
85 #clock-cells = <0>;
92 #size-cells = <0>;
94 cpu0: cpu@0 {
97 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
126 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw 0>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8280xp-microsoft-arcata.dts26 pinctrl-0 = <&wcd_default>;
53 #size-cells = <0>;
56 connector@0 {
58 reg = <0>;
64 #size-cells = <0>;
66 port@0 {
67 reg = <0>;
101 #size-cells = <0>;
103 port@0 {
104 reg = <0>;
[all …]
Dmsm8996-sony-xperia-tone.dtsi24 qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */
25 qcom,board-id = <8 0>;
34 reg = <0 0xa7f00000 0 0x100000>;
35 record-size = <0x20000>;
36 console-size = <0x40000>;
37 ftrace-size = <0x20000>;
38 pmsg-size = <0x20000>;
43 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
49 reg = <0x0 0x90400000 0x0 0x2000>;
54 reg = <0 0x90500000 0 0xa00000>;
[all …]
Dqcs8300.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0x0 0x0>;
66 reg = <0x0 0x100>;
85 reg = <0x0 0x200>;
104 reg = <0x0 0x300>;
123 reg = <0x0 0x10000>;
142 reg = <0x0 0x10100>;
[all …]
Dsc7280.dtsi81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/linux-6.15/drivers/scsi/bnx2i/
Dbnx2i.h94 #define ITT_INVALID_SIGNATURE 0xFFFF
110 #define CTX_OFFSET 0x10000
111 #define MAX_CID_CNT 0x4000
116 #define BNX2_MQ_CONFIG2 0x00003d00
117 #define BNX2_MQ_CONFIG2_CONT_SZ (0x7L<<4)
118 #define BNX2_MQ_CONFIG2_FIRST_L4L5 (0x1fL<<8)
126 #define CNIC_DISARM_CQE 0
140 } while (0)
151 } while (0)
163 } while (0)
[all …]
/linux-6.15/drivers/scsi/aic7xxx/
Daic79xx_osm.h84 #define AHD_DEBUG_OPTS 0
90 #define powerof2(x) ((((x)-1)&(x))==0)
149 #define BUS_DMA_WAITOK 0x0
150 #define BUS_DMA_NOWAIT 0x1
151 #define BUS_DMA_ALLOCNOW 0x2
152 #define BUS_DMA_LOAD_SEGS 0x4 /*
157 #define BUS_SPACE_MAXADDR 0xFFFFFFFF
158 #define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
159 #define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
191 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
[all …]
/linux-6.15/drivers/media/tuners/
Dxc4000.c29 MODULE_PARM_DESC(debug, "Debugging level (0 to 2, default: 0 (off)).");
33 MODULE_PARM_DESC(no_poweroff, "Power management (1: disabled, 2: enabled, 0 (default): use device-s…
46 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
107 #define XC_POWERED_DOWN 0x80000000U
110 #define XC_RF_MODE_AIR 0
114 #define XC_PRODUCT_ID_FW_NOT_LOADED 0x2000
115 #define XC_PRODUCT_ID_XC4000 0x0FA0
116 #define XC_PRODUCT_ID_XC4100 0x1004
119 #define XREG_INIT 0x00
120 #define XREG_VIDEO_MODE 0x01
[all …]
/linux-6.15/drivers/macintosh/
Dvia-cuda.c38 /* VIA registers - spaced 0x200 bytes apart */
39 #define RS 0x200 /* skip between registers */
40 #define B 0 /* B-side data */
75 #define TREQ 0x08 /* Transfer request */
76 #define TACK 0x10 /* Transfer acknowledge */
77 #define TIP 0x20 /* Transfer in progress */
80 #define SR_CTRL 0x1c /* Shift register control bits */
81 #define SR_EXT 0x0c /* Shift on external clock */
82 #define SR_OUT 0x10 /* Shift out if 1 */
85 #define IER_SET 0x80 /* set bits in IER */
[all …]
/linux-6.15/sound/soc/codecs/
Dwm2000.c54 ANC_ACTIVE = 0,
94 wm2000_write(i2c, WM2000_REG_ID1, 0); in wm2000_reset()
113 if (timeout == 0) in wm2000_poll_bit()
114 return 0; in wm2000_poll_bit()
132 if (ret != 0) { in wm2000_power_up()
175 if (ret < 0) { in wm2000_power_up()
203 if (ret != 0) { in wm2000_power_up()
214 wm2000_write(i2c, WM2000_REG_SYS_START0, 0x33); in wm2000_power_up()
215 wm2000_write(i2c, WM2000_REG_SYS_START1, 0x02); in wm2000_power_up()
231 return 0; in wm2000_power_up()
[all …]
/linux-6.15/drivers/net/wireless/broadcom/b43/
Dpio.c32 * Note that the cookie must never be 0, as this in generate_cookie()
34 * It can also not be 0xFFFF because that is special in generate_cookie()
52 switch (cookie & 0xF000) { in parse_cookie()
53 case 0x1000: in parse_cookie()
56 case 0x2000: in parse_cookie()
59 case 0x3000: in parse_cookie()
62 case 0x4000: in parse_cookie()
65 case 0x5000: in parse_cookie()
71 pack_index = (cookie & 0x0FFF); in parse_cookie()
112 return 0x18; in pio_txqueue_offset()
[all …]
/linux-6.15/drivers/staging/media/atomisp/include/linux/
Datomisp.h14 #define ATOMISP_HW_REVISION_MASK 0x0000ff00
16 #define ATOMISP_HW_REVISION_ISP2300 0x00
17 #define ATOMISP_HW_REVISION_ISP2400 0x10
18 #define ATOMISP_HW_REVISION_ISP2401_LEGACY 0x11
19 #define ATOMISP_HW_REVISION_ISP2401 0x20
21 #define ATOMISP_HW_STEPPING_MASK 0x000000ff
22 #define ATOMISP_HW_STEPPING_A0 0x00
23 #define ATOMISP_HW_STEPPING_B0 0x10
26 #define CI_MODE_PREVIEW 0x8000
27 #define CI_MODE_VIDEO 0x4000
[all …]
/linux-6.15/drivers/cpufreq/
Dtegra194-cpufreq.c24 #define MAX_CNT ~0U
28 #define NDIV_MASK 0x1FF
31 #define CMU_CLKS_BASE 0x2000
34 #define MMCRAB_CLUSTER_BASE(cl) (0x30000 + (cl * 0x10000))
130 return 0; in tegra234_get_cpu_ndiv()
147 * [31:0] Core clock counter: Counts on every core clock cycle
154 int cnt = 0; in tegra234_read_counters()
176 if (++cnt >= 0xFFFF) { in tegra234_read_counters()
193 .actmon_cntr_base = 0x9000,
201 .actmon_cntr_base = 0x4000,
[all …]
/linux-6.15/tools/testing/selftests/bpf/prog_tests/
Dflow_dissector.c11 #define FLOW_CONTINUE_SADDR 0x7f00007f /* 127.0.0.127 */
15 #define IP_MF 0x2000
295 .iph.flow_lbl = { 0xb, 0xee, 0xef },
308 .flow_label = __bpf_constant_htonl(0xbeeef),
318 .iph.flow_lbl = { 0xb, 0xee, 0xef },
330 .flow_label = __bpf_constant_htonl(0xbeeef),
341 .iph.flow_lbl = { 0x00, 0x00, 0x00 },
443 .flags = 0,
514 err = bpf_prog_attach(prog_fd, 0, BPF_FLOW_DISSECTOR, 0); in serial_test_flow_dissector_namespace()
528 err = bpf_prog_attach(prog_fd, 0, BPF_FLOW_DISSECTOR, 0); in serial_test_flow_dissector_namespace()
[all …]
/linux-6.15/arch/arm64/boot/dts/mediatek/
Dmt8186.dtsi35 reg = <0 0x1000ce00 0 0x200>;
336 #size-cells = <0>;
374 cpu0: cpu@0 {
377 reg = <0x000>;
401 reg = <0x100>;
425 reg = <0x200>;
449 reg = <0x300>;
473 reg = <0x400>;
497 reg = <0x500>;
521 reg = <0x600>;
[all …]
/linux-6.15/drivers/net/ethernet/realtek/
D8139too.c127 #define RTL8139_DEBUG 0
134 # define assert(expr) do {} while (0)
169 #define RX_BUF_IDX 0 /* 8K ring */
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
219 #define RTL_MIN_IO_SIZE 0x80
226 RTL8139 = 0,
[all …]
/linux-6.15/drivers/net/ethernet/sis/
Dsis900.c102 SIS_900 = 0,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_900},
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_7016},
115 {0,}
126 #define HOME 0x0001
127 #define LAN 0x0002
128 #define MIX 0x0003
129 #define UNKNOWN 0x0
131 { "SiS 900 Internal MII PHY", 0x001d, 0x8000, LAN },
132 { "SiS 7014 Physical Layer Solution", 0x0016, 0xf830, LAN },
[all …]
/linux-6.15/drivers/clk/qcom/
Dgcc-sm6125.c42 .offset = 0x0,
45 .enable_reg = 0x79000,
46 .enable_mask = BIT(0),
85 .offset = 0x3000,
88 .enable_reg = 0x79000,
102 .offset = 0x4000,
105 .enable_reg = 0x79000,
119 .offset = 0x5000,
122 .enable_reg = 0x79000,
136 .offset = 0x6000,
[all …]
/linux-6.15/drivers/parport/
Dparport_pc.c25 * base+0 data
33 * base+0x400 ECP config A
34 * base+0x401 ECP config B
35 * base+0x402 ECP control
42 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
85 #define ECR_MODE_MASK 0xe0
86 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
95 } superios[NR_SUPERIOS] = { {0,},};
111 unsigned char ectr = 0; in frob_econtrol()
114 if (m != 0xff) in frob_econtrol()
[all …]
/linux-6.15/arch/s390/net/
Dbpf_jit_comp.c61 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */
66 #define NVREGS 0xffc0 /* %r6-%r15 */
71 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
75 #define REG_0 REG_W0 /* Register 0 */
106 [REG_W0] = 0,
177 unsigned int __disp = (disp) & 0xfff; \
191 unsigned int __imm = (imm) & 0xffff; \
198 long __pcrel = ((pcrel) >> 1) & 0xffff; \
205 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \
219 unsigned int __disp = (disp) & 0xfff; \
[all …]
/linux-6.15/drivers/gpu/drm/rockchip/
Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux-6.15/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]

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