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/linux-6.15/arch/sh/include/asm/
Dsmc37c93x.h14 #define FDC_PRIMARY_BASE 0x3f0
15 #define IDE1_PRIMARY_BASE 0x1f0
16 #define IDE1_SECONDARY_BASE 0x170
17 #define PARPORT_PRIMARY_BASE 0x378
18 #define COM1_PRIMARY_BASE 0x2f8
19 #define COM2_PRIMARY_BASE 0x3f8
20 #define RTC_PRIMARY_BASE 0x070
21 #define KBC_PRIMARY_BASE 0x060
22 #define AUXIO_PRIMARY_BASE 0x000 /* XXX */
25 #define LDN_FDC 0
[all …]
/linux-6.15/arch/powerpc/boot/dts/
Dmpc866ads.dts19 #size-cells = <0>;
21 PowerPC,866@0 {
23 reg = <0x0>;
26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x800000>;
45 reg = <0xff000100 0x40>;
[all …]
Dtqm8xx.dts26 #size-cells = <0>;
28 PowerPC,860@0 {
30 reg = <0x0>;
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
45 reg = <0x0 0x2000000>;
52 reg = <0xfff00100 0x40>;
[all …]
/linux-6.15/include/linux/mfd/wm8994/
Dgpio.h15 #define WM8994_GP_FN_PIN_SPECIFIC 0
39 #define WM8994_GPN_DIR 0x8000 /* GPN_DIR */
40 #define WM8994_GPN_DIR_MASK 0x8000 /* GPN_DIR */
43 #define WM8994_GPN_PU 0x4000 /* GPN_PU */
44 #define WM8994_GPN_PU_MASK 0x4000 /* GPN_PU */
47 #define WM8994_GPN_PD 0x2000 /* GPN_PD */
48 #define WM8994_GPN_PD_MASK 0x2000 /* GPN_PD */
51 #define WM8994_GPN_POL 0x0400 /* GPN_POL */
52 #define WM8994_GPN_POL_MASK 0x0400 /* GPN_POL */
55 #define WM8994_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
[all …]
/linux-6.15/arch/arm/boot/dts/ti/omap/
Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
/linux-6.15/Documentation/devicetree/bindings/phy/
Dmediatek,mt8365-csi-rx.yaml32 enum: [0, 1]
34 If the PHY doesn't support mode selection then #phy-cells must be 0 and
66 reg = <0 0x11c10000 0 0x2000>;
73 reg = <0 0x11c12000 0 0x2000>;
76 #phy-cells = <0>;
/linux-6.15/arch/arm64/boot/dts/amlogic/
Dmeson-gx.dtsi35 hwrom_reserved: hwrom@0 {
36 reg = <0x0 0x0 0x0 0x1000000>;
42 reg = <0x0 0x10000000 0x0 0x200000>;
48 reg = <0x0 0x05000000 0x0 0x300000>;
54 reg = <0x0 0x05300000 0x0 0x2000000>;
61 size = <0x0 0x10000000>;
62 alignment = <0x0 0x400000>;
90 #address-cells = <0x2>;
91 #size-cells = <0x0>;
93 cpu0: cpu@0 {
[all …]
/linux-6.15/arch/m68k/include/asm/
Dtraps.h29 #define VEC_RESETSP (0)
100 #define PS_T (0x8000)
101 #define PS_S (0x2000)
102 #define PS_M (0x1000)
103 #define PS_C (0x0001)
107 #define FC (0x8000)
108 #define FB (0x4000)
109 #define RC (0x2000)
110 #define RB (0x1000)
111 #define DF (0x0100)
[all …]
DMC68EZ328.h27 * 0xFFFFF0xx -- System Control
34 #define SCR_ADDR 0xfffff000
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
38 #define SCR_DMAP 0x04 /* Double Map */
39 #define SCR_SO 0x08 /* Supervisor Only */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
41 #define SCR_PRV 0x20 /* Privilege Violation */
42 #define SCR_WPV 0x40 /* Write Protect Violation */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
48 #define MRR_ADDR 0xfffff004
[all …]
/linux-6.15/drivers/staging/gpib/hp_82335/
Dhp82335.h21 static const int hp82335_rom_size = 0x2000;
22 static const int hp82335_upper_iomem_size = 0x2000;
26 HPREG_CSR = 0x17f8,
27 HPREG_STATUS = 0x1ffc,
31 HPREG_INTR_CLEAR = 0x17f7,
36 DMA_ENABLE = (1 << 0), /* DMA enable */
43 SWITCH6 = (1 << 0), /* switch 6 position */
47 DMA_CHAN_STATUS = (1 << 5), /* DMA channel 0=3,1=2 */
/linux-6.15/include/uapi/linux/netfilter_ipv6/
Dip6t_srh.h9 #define IP6T_SRH_NEXTHDR 0x0001
10 #define IP6T_SRH_LEN_EQ 0x0002
11 #define IP6T_SRH_LEN_GT 0x0004
12 #define IP6T_SRH_LEN_LT 0x0008
13 #define IP6T_SRH_SEGS_EQ 0x0010
14 #define IP6T_SRH_SEGS_GT 0x0020
15 #define IP6T_SRH_SEGS_LT 0x0040
16 #define IP6T_SRH_LAST_EQ 0x0080
17 #define IP6T_SRH_LAST_GT 0x0100
18 #define IP6T_SRH_LAST_LT 0x0200
[all …]
/linux-6.15/Documentation/devicetree/bindings/dma/
Dfsl,mxs-dma.yaml81 reg = <0x80004000 0x2000>;
85 87 86 0 0>;
92 reg = <0x80024000 0x2000>;
93 interrupts = <78 79 66 0
/linux-6.15/Documentation/devicetree/bindings/sound/
Dqcom,wcd938x.yaml58 #size-cells = <0>;
59 reg = <0x03210000 0x2000>;
60 wcd938x_rx: codec@0,4 {
62 reg = <0 4>;
69 #size-cells = <0>;
70 reg = <0x03230000 0x2000>;
71 wcd938x_tx: codec@0,3 {
73 reg = <0 3>;
Dqcom,wcd937x.yaml43 pinctrl-0 = <&wcd_reset_n>;
62 reg = <0x03210000 0x2000>;
64 #size-cells = <0>;
65 wcd937x_rx: codec@0,4 {
67 reg = <0 4>;
73 reg = <0x03230000 0x2000>;
75 #size-cells = <0>;
76 wcd937x_tx: codec@0,3 {
78 reg = <0 3>;
/linux-6.15/arch/riscv/boot/dts/microchip/
Dmpfs-icicle-kit-fabric.dtsi10 reg = <0x0 0x40000000 0x0 0xF0>;
11 microchip,sync-update-mask = /bits/ 32 <0>;
19 reg = <0x0 0x40000200 0x0 0x100>;
21 #size-cells = <0>;
31 #address-cells = <0x3>;
32 #interrupt-cells = <0x1>;
33 #size-cells = <0x2>;
35 reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
36 <0x0 0x4300a000 0x0 0x2000>;
38 bus-range = <0x0 0x7f>;
[all …]
/linux-6.15/arch/sh/kernel/cpu/sh3/
Dclock-sh7706.c25 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); in master_clk_init()
37 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); in module_clk_recalc()
49 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); in bus_clk_recalc()
61 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); in cpu_clk_recalc()
Dclock-sh7709.c25 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); in master_clk_init()
37 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); in module_clk_recalc()
49 int idx = (frqcr & 0x0080) ? in bus_clk_recalc()
50 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1; in bus_clk_recalc()
62 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); in cpu_clk_recalc()
Dclock-sh3.c29 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); in master_clk_init()
41 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); in module_clk_recalc()
53 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); in bus_clk_recalc()
65 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); in cpu_clk_recalc()
/linux-6.15/arch/arm/boot/dts/realtek/
Drtd1195.dtsi6 /memreserve/ 0x00000000 0x0000a800; /* boot code */
7 /memreserve/ 0x0000a800 0x000f5800;
8 /memreserve/ 0x17fff000 0x00001000;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0x0>;
33 reg = <0x1>;
44 reg = <0x0000b000 0x1000>;
48 reg = <0x01b00000 0x400000>;
52 reg = <0x01ffe000 0x4000>;
[all …]
/linux-6.15/include/soc/fsl/
Dcpm.h54 u8 res6[0x22];
61 #define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
62 #define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
63 #define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
64 #define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
66 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
67 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
68 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
69 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
71 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
[all …]
/linux-6.15/arch/arm/boot/dts/samsung/
Dexynos5.dtsi40 reg = <0x10000000 0x100>;
45 reg = <0x12250000 0x14>;
53 reg = <0x10440000 0x1000>;
54 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x10481000 0x1000>,
93 <0x10482000 0x2000>,
94 <0x10484000 0x2000>,
95 <0x10486000 0x2000>;
102 reg = <0x10050000 0x5000>;
107 reg = <0x12c00000 0x100>;
[all …]
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgk104.c44 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x00000800, 0x00000800); in gk104_chan_stop()
52 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400); in gk104_chan_start()
60 nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x00000000); in gk104_chan_unbind()
68 nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x80000000 | chan->inst->addr >> 12); in gk104_chan_bind_inst()
77 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x000f0000, runl->id << 16); in gk104_chan_bind()
88 nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd)); in gk104_chan_ramfc_write()
89 nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd)); in gk104_chan_ramfc_write()
90 nvkm_wo32(chan->inst, 0x10, 0x0000face); in gk104_chan_ramfc_write()
91 nvkm_wo32(chan->inst, 0x30, 0xfffff902); in gk104_chan_ramfc_write()
92 nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset)); in gk104_chan_ramfc_write()
[all …]
Dgf100.c43 nvkm_wr32(chan->cgrp->runl->fifo->engine.subdev.device, 0x002634, chan->id); in gf100_chan_preempt()
51 nvkm_mask(device, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000); in gf100_chan_stop()
59 nvkm_wr32(device, 0x003004 + (chan->id * 8), 0x001f0001); in gf100_chan_start()
73 nvkm_wr32(device, 0x003000 + (chan->id * 8), 0x00000000); in gf100_chan_unbind()
81 nvkm_wr32(device, 0x003000 + (chan->id * 8), 0xc0000000 | chan->inst->addr >> 12); in gf100_chan_bind()
91 nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd)); in gf100_chan_ramfc_write()
92 nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd)); in gf100_chan_ramfc_write()
93 nvkm_wo32(chan->inst, 0x10, 0x0000face); in gf100_chan_ramfc_write()
94 nvkm_wo32(chan->inst, 0x30, 0xfffff902); in gf100_chan_ramfc_write()
95 nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset)); in gf100_chan_ramfc_write()
[all …]
/linux-6.15/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]

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