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/linux/arch/arm64/boot/dts/qcom/
H A Dsm8150-sony-xperia-kumano.dtsi26 qcom,msm-id = <339 0x20000>; /* SM8150 v2 */
27 qcom,board-id = <8 0>;
36 reg = <0 0x9c000000 0 0x2300000>;
55 pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>;
91 pinctrl-0 = <&main_cam_pwr_en>;
101 pinctrl-0 = <&sub_cam_pwr_en>;
111 pinctrl-0 = <&chat_cam_pwr_en>;
121 pinctrl-0 = <&supwc_pwr_en>;
131 pinctrl-0 = <&main_cam_pwr_vmdr_en>;
141 pinctrl-0 = <&rgbc_ir_pwr_en>;
[all …]
/linux/drivers/usb/host/
H A Dfhci-tds.c24 #define DUMMY_BD_BUFFER 0xdeadbeef
25 #define DUMMY2_BD_BUFFER 0xbaadf00d
28 #define TD_R 0x8000 /* ready bit */
29 #define TD_W 0x2000 /* wrap bit */
30 #define TD_I 0x1000 /* interrupt on completion */
31 #define TD_L 0x0800 /* last */
32 #define TD_TC 0x0400 /* transmit CRC */
33 #define TD_CNF 0x0200 /* CNF - Must be always 1 */
34 #define TD_LSP 0x0100 /* Low-speed transaction */
35 #define TD_PID 0x00c0 /* packet id */
[all …]
/linux/Documentation/driver-api/surface_aggregator/clients/
H A Ddtx.rst171 - ``0x0000``
175 - ``0x1000``
179 - ``0x2000``
183 - ``0xF000``
208 - ``0x1001``
213 - ``0x1002``
218 - ``0x2001``
223 - ``0x2002``
228 - ``0x2003``
245 - ``0x0000``
[all …]
/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpaa2-eth.h26 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
50 #define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF
113 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
120 * maximum 8 DPBP objects. By default, only the first DPBP (idx 0) is used for
124 #define DPAA2_ETH_DEFAULT_BP_IDX 0
129 * options are either 0 or 64, so we choose the latter.
176 #define DPAA2_FD_FRC_FASV 0x8000
177 #define DPAA2_FD_FRC_FAEADV 0x4000
178 #define DPAA2_FD_FRC_FAPRV 0x2000
179 #define DPAA2_FD_FRC_FAIADV 0x1000
[all …]
/linux/drivers/scsi/
H A Dfdomain.c97 * low as 0, or as high as 16. Note, however, that values which are too high
102 #define PARITY_MASK ACTL_PAREN /* Parity enabled, 0 = disabled */
105 unknown = 0x00,
106 tmc1800 = 0x01,
107 tmc18c50 = 0x02,
108 tmc18c30 = 0x03,
125 outb(0, fd->base + REG_BCTL); in fdomain_make_bus_idle()
126 outb(0, fd->base + REG_MCTL); in fdomain_make_bus_idle()
140 case 0x6127: in fdomain_identify()
142 case 0x60e9: /* 18c50 or 18c30 */ in fdomain_identify()
[all …]
/linux/drivers/firmware/cirrus/test/
H A Dcs_dsp_test_callbacks.c22 #define ADSP2_LOCK_REGION_CTRL 0x7A
23 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
50 .id = 0xfafa,
51 .ver = 0x100000,
75 return 0; in cs_dsp_test_control_add_callback()
97 return 0; in cs_dsp_test_pre_run_callback()
109 return 0; in cs_dsp_test_post_run_callback()
166 0); in cs_dsp_test_run_stop_callbacks()
168 KUNIT_EXPECT_EQ(test, cs_dsp_run(priv->dsp), 0); in cs_dsp_test_run_stop_callbacks()
171 KUNIT_EXPECT_EQ(test, local->num_pre_stop, 0); in cs_dsp_test_run_stop_callbacks()
[all …]
/linux/arch/m68k/include/asm/
H A Dm53xxsim.h40 #define MCF_WTM_WCR 0xFC098000
45 #define MCFSIM_IPRL 0xFC048004
46 #define MCFSIM_IPRH 0xFC048000
48 #define MCFSIM_IMRL 0xFC04800C
49 #define MCFSIM_IMRH 0xFC048008
51 #define MCFSIM_ICR0 0xFC048040
52 #define MCFSIM_ICR1 0xFC048041
53 #define MCFSIM_ICR2 0xFC048042
54 #define MCFSIM_ICR3 0xFC048043
55 #define MCFSIM_ICR4 0xFC048044
[all …]
/linux/drivers/video/fbdev/omap/
H A Dlcdc.c156 reset_count = 0; in reset_controller()
169 0, in setup_lcd_dma()
172 0, in setup_lcd_dma()
175 struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par; in setup_lcd_dma()
176 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var; in setup_lcd_dma()
183 case 0: in setup_lcd_dma()
287 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var; in omap_lcdc_setup_plane()
291 if (var->rotate == 0) { in omap_lcdc_setup_plane()
298 if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 || in omap_lcdc_setup_plane()
317 lcdc.palette_code = 0x3000; in omap_lcdc_setup_plane()
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_reg.h106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
122 #define GU_CNTL _MMIO(0x101010)
125 #define GU_DEBUG _MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
[all …]
/linux/drivers/clk/qcom/
H A Dcamcc-sdm845.c30 .offset = 0x0,
45 { 0x0, 1 },
46 { 0x1, 2 },
51 .offset = 0x0,
68 .offset = 0x1000,
83 .offset = 0x1000,
100 .offset = 0x2000,
115 .offset = 0x2000,
132 .offset = 0x3000,
147 .offset = 0x3000,
[all …]
H A Dcamcc-sm4450.c42 { 249600000, 2020000000, 0 },
46 { 864000000, 1056000000, 0 },
51 .l = 0x3e,
52 .alpha = 0x8000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00182261,
55 .config_ctl_hi1_val = 0x32aa299c,
56 .user_ctl_val = 0x00008400,
57 .user_ctl_hi_val = 0x00000805,
61 .offset = 0x0,
[all …]
H A Dcamcc-sc7180.c35 { 600000000, 3300000000UL, 0 },
39 { 249600000, 2000000000UL, 0 },
44 .l = 0x1f,
45 .alpha = 0x4000,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002067,
48 .test_ctl_val = 0x40000000,
49 .user_ctl_hi_val = 0x00004805,
50 .user_ctl_val = 0x00000001,
54 .offset = 0x0,
[all …]
/linux/sound/soc/codecs/
H A Dwm9713.c32 #define WM9713_VENDOR_ID 0x574d4c13
33 #define WM9713_VENDOR_ID_MASK 0xffffffff
43 #define HPL_MIXER 0
70 SOC_ENUM_SINGLE(AC97_LINE, 3, 4, wm9713_mic_mixer), /* record mic mixer 0 */
74 SOC_ENUM_SINGLE(AC97_VIDEO, 0, 8, wm9713_rec_src), /* record mux right 4*/
83 SOC_ENUM_SINGLE(AC97_REC_GAIN, 0, 4, wm9713_out4_pga), /* out 4 source 13 */
92 static const DECLARE_TLV_DB_SCALE(out_tlv, -4650, 150, 0);
93 static const DECLARE_TLV_DB_SCALE(main_tlv, -3450, 150, 0);
94 static const DECLARE_TLV_DB_SCALE(misc_tlv, -1500, 300, 0);
96 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
[all …]
H A Drt711-sdca.c37 if (ret < 0) in rt711_sdca_index_write()
53 if (ret < 0) in rt711_sdca_index_read()
68 if (ret < 0) in rt711_sdca_index_update_bits()
81 RT711_HDA_LEGACY_RESET_CTL, 0x1, 0x1); in rt711_sdca_reset()
87 case 0x00: in rt711_sdca_ge_force_jack_type()
88 rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG, RT711_COMBO_JACK_AUTO_CTL1, 0x8400, 0x0000); in rt711_sdca_ge_force_jack_type()
89 rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL, RT711_PUSH_BTN_INT_CTL0, 0x10, 0x00); in rt711_sdca_ge_force_jack_type()
91 case 0x03: in rt711_sdca_ge_force_jack_type()
92 rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG, RT711_COMBO_JACK_AUTO_CTL1, 0x8400, 0x8000); in rt711_sdca_ge_force_jack_type()
93 rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL, RT711_PUSH_BTN_INT_CTL0, 0x17, 0x13); in rt711_sdca_ge_force_jack_type()
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov920.dtsi38 #clock-cells = <0>;
44 #size-cells = <0>;
87 cpu0: cpu@0 {
90 reg = <0x0 0x0>;
92 i-cache-size = <0x10000>;
95 d-cache-size = <0x10000>;
104 reg = <0x0 0x100>;
106 i-cache-size = <0x10000>;
109 d-cache-size = <0x10000>;
118 reg = <0x0 0x200>;
[all …]
/linux/drivers/comedi/drivers/
H A Drtd520.c94 * Local Address Space 0 Offsets
96 #define LAS0_USER_IO 0x0008 /* User I/O */
97 #define LAS0_ADC 0x0010 /* FIFO Status/Software A/D Start */
98 #define FS_DAC1_NOT_EMPTY BIT(0) /* DAC1 FIFO not empty */
110 #define LAS0_UPDATE_DAC(x) (0x0014 + ((x) * 0x4)) /* D/Ax Update (w) */
111 #define LAS0_DAC 0x0024 /* Software Simultaneous Update (w) */
112 #define LAS0_PACER 0x0028 /* Software Pacer Start/Stop */
113 #define LAS0_TIMER 0x002c /* Timer Status/HDIN Software Trig. */
114 #define LAS0_IT 0x0030 /* Interrupt Status/Enable */
115 #define IRQM_ADC_FIFO_WRITE BIT(0) /* ADC FIFO Write */
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
/linux/drivers/ata/
H A Dsata_sx4.c89 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
91 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
92 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
93 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
94 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
96 PDC_CTLSTAT = 0x60, /* IDEn control / status */
98 PDC_20621_SEQCTL = 0x400,
99 PDC_20621_SEQMASK = 0x480,
100 PDC_20621_GENERAL_CTL = 0x484,
104 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
13 #define TW5864_H264REV 0x0000
15 #define TW5864_EMU 0x0004
18 #define TW5864_EMU_EN_DDR BIT(0)
40 #define TW5864_UNDECLARED_H264REV_PART2 0x0008
42 #define TW5864_SLICE 0x000c
45 #define TW5864_VLC_SLICE_END BIT(0)
52 * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
55 #define TW5864_ENC_BUF_PTR_REC1 0x0010
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]
H A Dmt8183.dtsi293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/linux/include/uapi/linux/
H A Drtnetlink.h235 #define RTA_DATA(rta) ((void*)(((char*)(rta)) + RTA_LENGTH(0)))
236 #define RTA_PAYLOAD(rta) ((int)((rta)->rta_len) - RTA_LENGTH(0))
284 #define RTPROT_UNSPEC 0
330 RT_SCOPE_UNIVERSE=0,
340 #define RTM_F_NOTIFY 0x100 /* Notify user of route change */
341 #define RTM_F_CLONED 0x200 /* This route is cloned */
342 #define RTM_F_EQUALIZE 0x400 /* Multipath equalizer: NI */
343 #define RTM_F_PREFIX 0x800 /* Prefix addresses */
344 #define RTM_F_LOOKUP_TABLE 0x1000 /* set rtm_table to FIB lookup result */
345 #define RTM_F_FIB_MATCH 0x2000 /* return full fib lookup match */
[all …]

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