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/linux-6.15/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dpsoc_global_conf_masks.h23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF
39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF
[all …]
/linux-6.15/arch/powerpc/boot/dts/fsl/
Dt4240rdb.dts56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0x00008000>;
61 nor@0,0 {
65 reg = <0x0 0x0 0x8000000>;
71 nand@2,0 {
75 reg = <0x2 0x0 0x10000>;
89 size = <0 0x1000000>;
90 alignment = <0 0x1000000>;
[all …]
Dmpc8536si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
53 /* controller at 0x9000 */
59 bus-range = <0 255>;
61 interrupts = <25 2 0 0>;
63 pcie@0 {
64 reg = <0 0 0 0 0>;
69 interrupts = <25 2 0 0>;
[all …]
/linux-6.15/arch/powerpc/boot/dts/
Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux-6.15/arch/arm/boot/dts/allwinner/
Dsun9i-a80.dtsi65 #size-cells = <0>;
67 cpu0: cpu@0 {
73 reg = <0x0>;
82 reg = <0x1>;
91 reg = <0x2>;
100 reg = <0x3>;
109 reg = <0x100>;
118 reg = <0x101>;
127 reg = <0x102>;
136 reg = <0x103>;
[all …]
Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
/linux-6.15/drivers/edac/
Daltera_edac.h15 #define CV_CTLCFG_OFST 0x00
18 #define CV_CTLCFG_ECC_EN 0x400
19 #define CV_CTLCFG_ECC_CORR_EN 0x800
20 #define CV_CTLCFG_GEN_SB_ERR 0x2000
21 #define CV_CTLCFG_GEN_DB_ERR 0x4000
26 #define CV_DRAMADDRW_OFST 0x2C
29 #define DRAMADDRW_COLBIT_MASK 0x001F
30 #define DRAMADDRW_COLBIT_SHIFT 0
31 #define DRAMADDRW_ROWBIT_MASK 0x03E0
33 #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
[all …]
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dtu102.c37 const u32 hoff = head * 0x800; in tu102_sor_dp_vcpi()
39 nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn); in tu102_sor_dp_vcpi()
40 nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot); in tu102_sor_dp_vcpi()
49 u32 dpctrl = 0x00000000; in tu102_sor_dp_links()
50 u32 clksor = 0x00000000; in tu102_sor_dp_links()
55 dpctrl |= 0x40000000; in tu102_sor_dp_links()
57 dpctrl |= 0x00004000; in tu102_sor_dp_links()
59 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); in tu102_sor_dp_links()
63 nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000); in tu102_sor_dp_links()
64 nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001); in tu102_sor_dp_links()
[all …]
/linux-6.15/arch/arm/boot/dts/amlogic/
Dmeson.dtsi28 reg = <0xc1100000 0x200000>;
31 ranges = <0x0 0xc1100000 0x200000>;
37 reg = <0x4000 0x400>;
44 reg = <0x5400 0x2ac>;
53 reg = <0x7c00 0x200>;
58 reg = <0x8100 0x8>;
63 reg = <0x84c0 0x18>;
71 reg = <0x84dc 0x18>;
78 reg = <0x8500 0x20>;
81 #size-cells = <0>;
[all …]
/linux-6.15/drivers/net/wireless/ath/carl9170/
Dwlan.h44 #define AR9170_RX_PHY_RATE_CCK_1M 0x0a
45 #define AR9170_RX_PHY_RATE_CCK_2M 0x14
46 #define AR9170_RX_PHY_RATE_CCK_5M 0x37
47 #define AR9170_RX_PHY_RATE_CCK_11M 0x6e
49 #define AR9170_ENC_ALG_NONE 0x0
50 #define AR9170_ENC_ALG_WEP64 0x1
51 #define AR9170_ENC_ALG_TKIP 0x2
52 #define AR9170_ENC_ALG_AESCCMP 0x4
53 #define AR9170_ENC_ALG_WEP128 0x5
54 #define AR9170_ENC_ALG_WEP256 0x6
[all …]
/linux-6.15/arch/powerpc/kernel/
Dhead_book3s_32.S41 li RA,0; \
44 lwz RA,(n*16)+0(reg); \
73 * 0, running with virtual == physical mapping.
78 * from 0x380000 - 0x400000, which is mapped in already.
82 * r3: 'BooX' (0x426f6f58)
84 * r5: 0
91 * r4: initrd_start or if no initrd then 0
92 * r5: initrd_end - unused if r4 is 0
108 cmpwi 0,r5,0
114 0: mflr r8 /* r8 = runtime addr here */
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/core/
Ddc_hw_sequencer.c36 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
41 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
62 {0, 0, 0},
64 {0x40, 0x40, 0x40},
66 {0x200, 0x40, 0x200},
68 {0x1f4, 0x40, 0x1f4},
70 {0x1a2, 0x20, 0x1a2},
72 {0xff, 0xff, 0},
82 { 0x2000, 0, 0, 0,
83 0, 0x2000, 0, 0,
[all …]
/linux-6.15/drivers/net/wireless/broadcom/b43legacy/
Dphy.c33 0x4D, 0x4C, 0x4B, 0x4A,
34 0x4A, 0x49, 0x48, 0x47,
35 0x47, 0x46, 0x45, 0x45,
36 0x44, 0x43, 0x42, 0x42,
37 0x41, 0x40, 0x3F, 0x3E,
38 0x3D, 0x3C, 0x3B, 0x3A,
39 0x39, 0x38, 0x37, 0x36,
40 0x35, 0x34, 0x32, 0x31,
41 0x30, 0x2F, 0x2D, 0x2C,
42 0x2B, 0x29, 0x28, 0x26,
[all …]
/linux-6.15/arch/mips/boot/dts/ingenic/
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/linux-6.15/arch/arm/boot/dts/ti/omap/
Domap2.dtsi29 #address-cells = <0>;
30 #size-cells = <0>;
61 reg = <0x480a6000 0x50>;
69 reg = <0x480b2000 0x1000>;
77 reg = <0x480FE000 0x1000>;
82 reg = <0x48056000 0x4>,
83 <0x4805602c 0x4>,
84 <0x48056028 0x4>;
98 ranges = <0 0x48056000 0x1000>;
100 sdma: dma-controller@0 {
[all …]
/linux-6.15/drivers/net/ethernet/rdc/
Dr6040.c50 #define MCR0 0x00 /* Control register 0 */
51 #define MCR0_RCVEN 0x0002 /* Receive enable */
52 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
53 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
54 #define MCR0_XMTEN 0x1000 /* Transmission enable */
55 #define MCR0_FD 0x8000 /* Full/Half duplex */
56 #define MCR1 0x04 /* Control register 1 */
57 #define MAC_RST 0x0001 /* Reset the MAC */
58 #define MBCR 0x08 /* Bus control */
59 #define MT_ICR 0x0C /* TX interrupt control */
[all …]
/linux-6.15/drivers/net/ethernet/broadcom/
Dcnic.h32 #define L5_KRNLQ_FLAGS 0x00000000
33 #define L5_KRNLQ_SIZE 0x00000000
34 #define L5_KRNLQ_TYPE 0x00000000
35 #define KRNLQ_FLAGS_PG_SZ (0xf<<0)
36 #define KRNLQ_FLAGS_PG_SZ_256 (0<<0)
37 #define KRNLQ_FLAGS_PG_SZ_512 (1<<0)
38 #define KRNLQ_FLAGS_PG_SZ_1K (2<<0)
39 #define KRNLQ_FLAGS_PG_SZ_2K (3<<0)
40 #define KRNLQ_FLAGS_PG_SZ_4K (4<<0)
41 #define KRNLQ_FLAGS_PG_SZ_8K (5<<0)
[all …]
/linux-6.15/arch/m68k/include/asm/
Dfbio.h13 #define FBTYPE_SUN1BW 0 /* mono */
58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)
61 int index; /* first element (0 origin) */
124 #define FB_WID_SHARED_8 0
196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
225 #define CG6_FBC 0x70000000
226 #define CG6_TEC 0x70001000
227 #define CG6_BTREGS 0x70002000
228 #define CG6_FHC 0x70004000
229 #define CG6_THC 0x70005000
[all …]
/linux-6.15/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/linux-6.15/include/linux/
Dswitchtec.h16 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
17 #define SWITCHTEC_EVENT_CLEAR BIT(0)
24 #define SWITCHTEC_DMA_MRPC_EN BIT(0)
26 #define MRPC_GAS_READ 0x29
27 #define MRPC_GAS_WRITE 0x87
28 #define MRPC_CMD_ID(x) ((x) & 0xffff)
31 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
32 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
33 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
34 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
[all …]
/linux-6.15/sound/mips/
Dsnd-n64.c31 #define AI_ADDR_REG 0
41 #define MI_INTR_AI 0x04
43 #define MI_MASK_CLR_AI 0x0010
44 #define MI_MASK_SET_AI 0x0020
161 int changed = 0; in hw_rule_period_size()
164 * The DMA unit has errata on (start + len) & 0x3fff == 0x2000. in hw_rule_period_size()
193 if (err < 0) in n64audio_pcm_open()
196 err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); in n64audio_pcm_open()
197 if (err < 0) in n64audio_pcm_open()
200 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, in n64audio_pcm_open()
[all …]
/linux-6.15/drivers/phy/socionext/
Dphy-uniphier-pcie.c22 #define PCL_PHY_CLKCTRL 0x0000
26 #define PCL_PHY_TEST_I 0x2000
29 #define TESTI_WR_EN BIT(0)
32 #define PCL_PHY_TEST_O 0x2004
33 #define TESTO_DAT_MASK GENMASK(7, 0)
35 #define PCL_PHY_RESET 0x200c
37 #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */
40 #define SG_USBPCIESEL 0x590
41 #define SG_USBPCIESEL_PCIE BIT(0)
44 #define SC_US3SRCSEL 0x2244
[all …]
/linux-6.15/sound/soc/amd/acp/
Dacp-platform.c116 stream->reg_offset = 0x02000000; in config_pte_for_stream()
127 writel(0x01, chip->base + ACPAXI2AXI_ATU_CTRL); in config_pte_for_stream()
146 val = 0x0; in config_acp_dma()
148 val = 0x1000; in config_acp_dma()
152 val = 0x2000; in config_acp_dma()
154 val = 0x3000; in config_acp_dma()
158 val = 0x4000; in config_acp_dma()
160 val = 0x5000; in config_acp_dma()
163 val = 0x6000; in config_acp_dma()
175 for (page_idx = 0; page_idx < num_pages; page_idx++) { in config_acp_dma()
[all …]
/linux-6.15/arch/arm64/boot/dts/renesas/
Dr8a77951.dtsi23 * The external audio clocks are configured as 0 Hz fixed frequency
29 #clock-cells = <0>;
30 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
52 cluster0_opp: opp-table-0 {
[all …]
/linux-6.15/arch/powerpc/boot/
Drs6000.h70 #define RS6K_AOUTHDR_OMAGIC 0x0107 /* old: text & data writeable */
71 #define RS6K_AOUTHDR_NMAGIC 0x0108 /* new: text r/o, data r/w */
72 #define RS6K_AOUTHDR_ZMAGIC 0x010B /* paged: text r/o, both page-aligned */
104 #define STYP_LOADER 0x1000
107 #define STYP_DEBUG 0x2000
111 #define STYP_OVRFLO 0x8000
117 * grouping will have l_lnno = 0 and in place of physical address will be the
122 char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/
221 #define DBXMASK 0x80 /* for dbx storage mask */

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