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/src/sys/contrib/device-tree/src/mips/mti/
H A Dsead3.dts4 /memreserve/ 0x00000000 0x00001000; // reserved
5 /memreserve/ 0x00001000 0x000ef000; // ROM data
6 /memreserve/ 0x000f0000 0x004cc000; // reserved
26 cpu@0 {
33 reg = <0x0 0x08000000>;
45 reg = <0x1b1c0000 0x20000>;
61 reg = <0x1b200000 0x1000>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
71 reg = <0x1c000000 0x2000000>;
81 user-fs@0 {
[all …]
/src/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,sm8550-tcsr.yaml58 reg = <0x1fc0000 0x30000>;
/src/sys/contrib/device-tree/Bindings/remoteproc/
H A Drenesas,rcar-rproc.yaml54 reg = <0x0 0x40040000 0x0 0x1fc0000>;
/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
/src/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dqcs8300.dtsi30 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
68 reg = <0x0 0x100>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
88 reg = <0x0 0x200>;
108 reg = <0x0 0x300>;
[all …]
H A Dsm8450.dtsi40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 cpu0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
H A Dsa8775p.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]