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/linux-6.8/drivers/regulator/
Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/linux-6.8/arch/arm/mach-omap2/
Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/linux-6.8/drivers/net/ethernet/qualcomm/
Dqca_7k.h35 #define QCA7K_SPI_WRITE (0 << 15)
37 #define QCA7K_SPI_EXTERNAL (0 << 14)
41 #define QCASPI_HW_BUF_LEN 0xC5B
44 #define SPI_REG_BFR_SIZE 0x0100
45 #define SPI_REG_WRBUF_SPC_AVA 0x0200
46 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
47 #define SPI_REG_SPI_CONFIG 0x0400
48 #define SPI_REG_SPI_STATUS 0x0500
49 #define SPI_REG_INTR_CAUSE 0x0C00
50 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/linux-6.8/drivers/net/wireless/broadcom/b43/
Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
/linux-6.8/arch/arm/boot/dts/ti/omap/
Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
/linux-6.8/drivers/gpu/drm/rockchip/
Drockchip_vop2_reg.c138 .id = 0,
144 .offset = 0xc00,
150 .offset = 0xd00,
156 .offset = 0xe00,
181 .base = 0x1c00,
197 .base = 0x1e00,
210 .base = 0x1a00,
223 .base = 0x1800,
233 .base = 0x1000,
237 .layer_sel_id = 0,
[all …]
/linux-6.8/drivers/block/
Dswim_asm.S17 .equ write_data, 0x0000
18 .equ write_mark, 0x0200
19 .equ write_CRC, 0x0400
20 .equ write_parameter,0x0600
21 .equ write_phase, 0x0800
22 .equ write_setup, 0x0a00
23 .equ write_mode0, 0x0c00
24 .equ write_mode1, 0x0e00
25 .equ read_data, 0x1000
26 .equ read_mark, 0x1200
[all …]
/linux-6.8/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_5_4_sm6125.h13 .max_mixer_blendstages = 0x6,
24 .base = 0x0, .len = 0x45c,
25 .features = 0,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
36 .base = 0x1000, .len = 0x1e0,
41 .base = 0x1200, .len = 0x1e0,
46 .base = 0x1400, .len = 0x1e0,
51 .base = 0x1600, .len = 0x1e0,
[all …]
/linux-6.8/sound/soc/amd/acp/
Dacp70.c10 * Hardware interface for ACP7.0 block
29 .offset = 0,
33 .irq_reg_offset = 0x1a00,
34 .i2s_pin_cfg_offset = 0x1440,
35 .i2s_mode = 0x0a,
36 .scratch_reg_offset = 0x12800,
37 .sram_pte_offset = 0x03802800,
195 return 0; in acp_acp70_audio_probe()
233 return 0; in acp70_pcm_resume()
Dacp63.c29 #define CLK_PLL_PWR_REQ_N0 0X0006C2C0
30 #define CLK_SPLL_FIELD_2_N0 0X0006C114
31 #define CLK_PLL_REQ_N0 0X0006C0DC
32 #define CLK_DFSBYPASS_CONTR 0X0006C2C8
33 #define CLK_DFS_CNTL_N0 0X0006C1A4
36 #define PLL_AUTO_START_REQ BIT(0)
40 #define CLK0_DIVIDER 0X30
53 .offset = 0,
57 .irq_reg_offset = 0x1a00,
58 .i2s_pin_cfg_offset = 0x1440,
[all …]
Dacp-rembrandt.c31 #define MP1_C2PMSG_69 0x3B10A14
32 #define MP1_C2PMSG_85 0x3B10A54
33 #define MP1_C2PMSG_93 0x3B10A74
34 #define HOST_BRIDGE_ID 0x14B5
37 .offset = 0,
41 .irq_reg_offset = 0x1a00,
42 .i2s_pin_cfg_offset = 0x1440,
43 .i2s_mode = 0x0a,
44 .scratch_reg_offset = 0x12800,
45 .sram_pte_offset = 0x03802800,
[all …]
/linux-6.8/drivers/net/wireless/broadcom/b43legacy/
Dradio.c30 0x0002, 0x0003, 0x0001, 0x000F,
31 0x0006, 0x0007, 0x0005, 0x000F,
32 0x000A, 0x000B, 0x0009, 0x000F,
33 0x000E, 0x000F, 0x000D, 0x000F,
41 u16 flipped = 0x0000; in flip_4bit()
43 B43legacy_BUG_ON(!((value & ~0x000F) == 0x0000)); in flip_4bit()
45 flipped |= (value & 0x0001) << 3; in flip_4bit()
46 flipped |= (value & 0x0002) << 1; in flip_4bit()
47 flipped |= (value & 0x0004) >> 1; in flip_4bit()
48 flipped |= (value & 0x0008) >> 3; in flip_4bit()
[all …]
/linux-6.8/arch/x86/boot/
Dvideo-vga.c18 { VIDEO_80x25, 80, 25, 0 },
19 { VIDEO_8POINT, 80, 50, 0 },
20 { VIDEO_80x43, 80, 43, 0 },
21 { VIDEO_80x28, 80, 28, 0 },
22 { VIDEO_80x30, 80, 30, 0 },
23 { VIDEO_80x34, 80, 34, 0 },
24 { VIDEO_80x60, 80, 60, 0 },
28 { VIDEO_80x25, 80, 25, 0 },
29 { VIDEO_8POINT, 80, 43, 0 },
33 { VIDEO_80x25, 80, 25, 0 },
[all …]
/linux-6.8/arch/arm/plat-orion/
Dpcie.c22 #define PCIE_DEV_ID_OFF 0x0000
23 #define PCIE_CMD_OFF 0x0004
24 #define PCIE_DEV_REV_OFF 0x0008
25 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
26 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
27 #define PCIE_HEADER_LOG_4_OFF 0x0128
28 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
29 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
30 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
31 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
[all …]
/linux-6.8/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/linux-6.8/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.c287 .base = 0xa00, .len = 0xa0,}, \
289 .base = 0x1a00, .len = 0x100,}, \
303 .base = 0xa00, .len = 0xa0,}, \
305 .base = 0x1a00, .len = 0x100,}, \
355 _VIG_SBLK(SSPP_SCALER_VER(3, 0));
358 _VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0),
382 0x20, 0x50, 0x80, 0xb0, 0x230,
383 0x260, 0x290
393 0x20, 0x38, 0x50, 0x68, 0x80, 0x98,
394 0xb0, 0xc8, 0xe0, 0xf8, 0x110
[all …]
/linux-6.8/include/video/
Daty128.h13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
/linux-6.8/drivers/net/ethernet/microchip/
Denc28j60_hw.h15 * - Register address (bits 0-4)
19 #define ADDR_MASK 0x1F
20 #define BANK_MASK 0x60
21 #define SPRD_MASK 0x80
23 #define EIE 0x1B
24 #define EIR 0x1C
25 #define ESTAT 0x1D
26 #define ECON2 0x1E
27 #define ECON1 0x1F
28 /* Bank 0 registers */
[all …]
/linux-6.8/arch/loongarch/boot/dts/
Dloongson-2k2000.dtsi16 #size-cells = <0>;
21 reg = <0x0>;
28 reg = <0x1>;
35 #clock-cells = <0>;
47 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
48 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
49 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
50 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
56 reg = <0x0 0x100d0000 0x0 0x58>;
59 loongson,suspend-address = <0x0 0x1c000500>;
[all …]
/linux-6.8/drivers/net/ethernet/sis/
Dsis190.c40 #define PHY_ID_ANY 0x1f
41 #define MII_REG_ANY 0x1f
55 #define RX_BUF_MASK 0xfff8
57 #define SIS190_REGS_SIZE 0x80
65 #define EhnMIIread 0x0000
66 #define EhnMIIwrite 0x0020
70 #define EhnMIIreq 0x0010
71 #define EhnMIInotDone 0x0010
84 TxControl = 0x00,
85 TxDescStartAddr = 0x04,
[all …]
/linux-6.8/drivers/media/i2c/
Dhi847.c25 #define HI847_REG_CHIP_ID 0x0716
26 #define HI847_CHIP_ID 0x0847
28 #define HI847_REG_MODE_SELECT 0x0B00
29 #define HI847_MODE_STANDBY 0x0000
30 #define HI847_MODE_STREAMING 0x0100
32 #define HI847_REG_MODE_TG 0x027E
33 #define HI847_REG_MODE_TG_ENABLE 0x0100
34 #define HI847_REG_MODE_TG_DISABLE 0x0000
37 #define HI847_REG_FLL 0x020E
38 #define HI847_FLL_30FPS 0x0B51
[all …]
/linux-6.8/drivers/media/pci/cx25821/
Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/linux-6.8/drivers/net/wireless/realtek/rtw88/
Drtw8822c.h11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 res0[0x4a]; /* 0x120 */
21 u8 mac_addr[ETH_ALEN]; /* 0x16a */
25 u8 mac_addr[ETH_ALEN]; /* 0x120 */
33 u8 ltr_cap; /* 0x133 */
38 u8 res0:2; /* 0x144 */
62 u8 res0[0x0e];
[all …]

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