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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
H A Dbnx2x_self_test.c6 #define NA 0xCD
8 #define IDLE_CHK_E1 0x01
9 #define IDLE_CHK_E1H 0x02
10 #define IDLE_CHK_E2 0x04
11 #define IDLE_CHK_E3A0 0x08
12 #define IDLE_CHK_E3B0 0x10
118 /*line 2*/{(0x3), 1, 0x2114,
119 NA, 1, 0, pand_neq,
121 "PCIE: ucorr_err_status is not 0",
122 {NA, NA, 0x0FF010, 0, NA, NA} },
[all …]
/linux/drivers/media/platform/verisilicon/
H A Dhantro_g2_regs.h22 #define G2_REG_VERSION G2_SWREG(0)
28 #define G2_REG_INTERRUPT_DEC_E BIT(0)
30 #define HEVC_DEC_MODE 0xc
31 #define VP9_DEC_MODE 0xd
33 #define BUS_WIDTH_32 0
38 #define g2_strm_swap G2_DEC_REG(2, 28, 0xf)
39 #define g2_strm_swap_old G2_DEC_REG(2, 27, 0x1f)
40 #define g2_pic_swap G2_DEC_REG(2, 22, 0x1f)
41 #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf)
42 #define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f)
[all …]
H A Dhantro_g1_regs.h15 #define G1_REG_INTERRUPT 0x004
26 #define G1_REG_INTERRUPT_DEC_E BIT(0)
27 #define G1_REG_CONFIG 0x008
28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24)
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11)
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5)
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0)
46 #define G1_REG_DEC_CTRL0 0x00c
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28)
70 #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0)
[all …]
H A Drockchip_vpu2_regs.h13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
/linux/sound/soc/
H A Dsoc-ops-test.c24 .reg = 0, .shift = 0, .sign_bit = xsign, .invert = xinvert, \
25 .rreg = SOC_OPS_TEST_##clayout == SOC_OPS_TEST_DOUBLE_R ? 1 : 0, \
26 .rshift = SOC_OPS_TEST_##clayout == SOC_OPS_TEST_DOUBLE ? 16 : 0, \
59 .rmask = SOC_OPS_TEST_##clayout == SOC_OPS_TEST_DOUBLE_R ? (xmask) : 0, \
60 .init = cinit ? 0xFFFFFFFF : 0x00000000, \
63 .rreg = SOC_OPS_TEST_##clayout == SOC_OPS_TEST_DOUBLE_R ? (xreg) : 0, \
102 ITEST("Test Control", SINGLE, BOOLEAN, volsw, 0, 1, 0, 1, 0, 0, 0),
103 ITEST("Test Volume", SINGLE, INTEGER, volsw, 0, 1, 0, 1, 0, 0, 0),
104 ITEST("Test Volume Control", SINGLE, BOOLEAN, volsw, 0, 1, 0, 1, 0, 0, 0),
105 ITEST("Test Control", DOUBLE_R, BOOLEAN, volsw, 0, 1, 0, 1, 0, 0, 0),
[all …]
/linux/sound/soc/codecs/
H A Des8375.c42 static const DECLARE_TLV_DB_SCALE(es8375_adc_osr_gain_tlv, -3100, 100, 0);
43 static const DECLARE_TLV_DB_SCALE(es8375_adc_volume_tlv, -9550, 50, 0);
44 static const DECLARE_TLV_DB_SCALE(es8375_adc_automute_attn_tlv, 0, 100, 0);
45 static const DECLARE_TLV_DB_SCALE(es8375_adc_dmic_volume_tlv, 0, 600, 0);
46 static const DECLARE_TLV_DB_SCALE(es8375_dac_volume_tlv, -9550, 50, 0);
47 static const DECLARE_TLV_DB_SCALE(es8375_dac_vppscale_tlv, -388, 12, 0);
48 static const DECLARE_TLV_DB_SCALE(es8375_dac_automute_attn_tlv, 0, 400, 0);
49 static const DECLARE_TLV_DB_SCALE(es8375_automute_ng_tlv, -9600, 600, 0);
111 ADC_OSR_GAIN_SHIFT_0, ES8375_ADC_OSR_GAIN_MAX, 0,
113 SOC_SINGLE("ADC Invert Switch", ES8375_ADC1, ADC_INV_SHIFT_6, 1, 0),
[all …]
H A Dda7218.h21 #define DA7218_SYSTEM_ACTIVE 0x0
22 #define DA7218_CIF_CTRL 0x1
23 #define DA7218_CHIP_ID1 0x4
24 #define DA7218_CHIP_ID2 0x5
25 #define DA7218_CHIP_REVISION 0x6
26 #define DA7218_SPARE1 0x7
27 #define DA7218_STATUS1 0x8
28 #define DA7218_SOFT_RESET 0x9
29 #define DA7218_SR 0xB
30 #define DA7218_PC_COUNT 0xC
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-leadtek-ltk050h3146w.c42 { 0x22, 0x0A }, /* BGR SS GS */
43 { 0x31, 0x00 }, /* column inversion */
44 { 0x53, 0xA2 }, /* VCOM1 */
45 { 0x55, 0xA2 }, /* VCOM2 */
46 { 0x50, 0x81 }, /* VREG1OUT=5V */
47 { 0x51, 0x85 }, /* VREG2OUT=-5V */
48 { 0x62, 0x0D }, /* EQT Time setting */
53 { 0xA0, 0x00 },
54 { 0xA1, 0x1A },
55 { 0xA2, 0x28 },
[all …]
H A Dpanel-samsung-s6e8aa0.c34 #define PANELCTL_SS_1_800 (0 << 5)
41 #define PANELCTL_CLK1_000 (0 << 3)
43 #define PANELCTL_CLK2_CON_MASK (7 << 0)
44 #define PANELCTL_CLK2_000 (0 << 0)
45 #define PANELCTL_CLK2_001 (1 << 0)
48 #define PANELCTL_INT1_000 (0 << 3)
50 #define PANELCTL_INT2_CON_MASK (7 << 0)
51 #define PANELCTL_INT2_000 (0 << 0)
52 #define PANELCTL_INT2_001 (1 << 0)
55 #define PANELCTL_BICTL_000 (0 << 3)
[all …]
H A Dpanel-visionox-rm69299.c39 { 0xfe, 0x00 }, { 0xc2, 0x08 }, { 0x35, 0x00 }, { 0x51, 0xff },
43 { 0xfe, 0x40 }, { 0x05, 0x04 }, { 0x06, 0x08 }, { 0x08, 0x04 },
44 { 0x09, 0x08 }, { 0x0a, 0x07 }, { 0x0b, 0xcc }, { 0x0c, 0x07 },
45 { 0x0d, 0x90 }, { 0x0f, 0x87 }, { 0x20, 0x8d }, { 0x21, 0x8d },
46 { 0x24, 0x05 }, { 0x26, 0x05 }, { 0x28, 0x05 }, { 0x2a, 0x05 },
47 { 0x2d, 0x28 }, { 0x2f, 0x28 }, { 0x30, 0x32 }, { 0x31, 0x32 },
48 { 0x37, 0x80 }, { 0x38, 0x30 }, { 0x39, 0xa8 }, { 0x46, 0x48 },
49 { 0x47, 0x48 }, { 0x6b, 0x10 }, { 0x6f, 0x02 }, { 0x74, 0x2b },
50 { 0x80, 0x1a }, { 0xfe, 0x40 }, { 0x93, 0x10 }, { 0x16, 0x00 },
51 { 0x85, 0x07 }, { 0x84, 0x01 }, { 0x86, 0x0f }, { 0x87, 0x05 },
[all …]
H A Dpanel-jadard-jd9365da-h3.c48 #define JD9365DA_DCS_SWITCH_PAGE 0xe0
55 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe1, 0x93); in jadard_enable_standard_cmds()
56 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe2, 0x65); in jadard_enable_standard_cmds()
57 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe3, 0xf8); in jadard_enable_standard_cmds()
58 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03); in jadard_enable_standard_cmds()
112 gpiod_set_value(jadard->reset, 0); in jadard_prepare()
118 gpiod_set_value(jadard->reset, 0); in jadard_prepare()
125 return 0; in jadard_prepare()
132 gpiod_set_value(jadard->reset, 0); in jadard_unprepare()
144 return 0; in jadard_unprepare()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_aic.c25 0, 3, 9, 15, 21, 27
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
73 if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0)) in ar9003_aic_find_valid()
80 * type 0: aic_lin_table, 1: com_att_db_table
86 if (type == 0) { in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
92 for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) { in ar9003_aic_find_index()
111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
115 aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dvpe_regs.h16 #define VPE_PID 0x0000
17 #define VPE_PID_MINOR_MASK 0x3f
18 #define VPE_PID_MINOR_SHIFT 0
19 #define VPE_PID_CUSTOM_MASK 0x03
21 #define VPE_PID_MAJOR_MASK 0x07
23 #define VPE_PID_RTL_MASK 0x1f
25 #define VPE_PID_FUNC_MASK 0xfff
27 #define VPE_PID_SCHEME_MASK 0x03
30 #define VPE_SYSCONFIG 0x0010
31 #define VPE_SYSCONFIG_IDLE_MASK 0x03
[all …]
/linux/sound/soc/amd/include/
H A Dacp_2_2_sh_mask.h27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
[all …]
/linux/arch/powerpc/math-emu/
H A Dmath.c29 void *op4) { return 0; }
80 #define OP31 0x1f /* 31 */
81 #define LFS 0x30 /* 48 */
82 #define LFSU 0x31 /* 49 */
83 #define LFD 0x32 /* 50 */
84 #define LFDU 0x33 /* 51 */
85 #define STFS 0x34 /* 52 */
86 #define STFSU 0x35 /* 53 */
87 #define STFD 0x36 /* 54 */
88 #define STFDU 0x37 /* 55 */
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h6 #define DE_STATE1 0x100054
7 #define DE_STATE1_DE_ABORT BIT(0)
9 #define DE_STATE2 0x100058
14 #define SYSTEM_CTRL 0x000000
15 #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30)
16 #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30)
17 #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30)
18 #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30)
19 #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30)
35 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_2_0_0_sh_mask.h27 …S_CNTL__DISABLE_ATC__SHIFT 0x0
28 …S_CNTL__DISABLE_PRI__SHIFT 0x1
29 …S_CNTL__DISABLE_PASID__SHIFT 0x2
30 …S_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
31 …_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
32 …_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
33 …_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
34 …DISABLE_ATC_MASK 0x00000001L
35 …DISABLE_PRI_MASK 0x00000002L
36 …DISABLE_PASID_MASK 0x00000004L
[all …]
H A Dathub_2_1_0_sh_mask.h27 …ATS_MODE_CNTL__HOST_TRANS_ENABLE__SHIFT 0x0
28 …ATS_MODE_CNTL__CONSOLE_IOV_ENABLE__SHIFT 0x1
29 …_CNTL__HOST_TRANS_ENABLE_MASK 0x00000001L
30 …_CNTL__CONSOLE_IOV_ENABLE_MASK 0x00000002L
32 …SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
33 …HARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
34 …IRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
35 …IRT_RESET_REQ__PF_MASK 0x80000000L
37 …SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
38 …HARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
[all …]
H A Dathub_1_0_sh_mask.h27 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
28 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
29 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
30 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
31 #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
32 #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
33 #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
34 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
35 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
36 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
[all …]
/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_masks.h15 ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
16 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
17 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
20 ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
21 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
22 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
23 (0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT))
26 (0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT)
29 ((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \
30 (0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT))
[all …]
/linux/drivers/video/fbdev/sis/
H A Doem300.h55 {0x08,0x08,0x08,0x08},
56 {0x08,0x08,0x08,0x08},
57 {0x08,0x08,0x08,0x08},
58 {0x2c,0x2c,0x2c,0x2c},
59 {0x08,0x08,0x08,0x08},
60 {0x08,0x08,0x08,0x08},
61 {0x08,0x08,0x08,0x08},
62 {0x20,0x20,0x20,0x20}
67 {0x20,0x20,0x20,0x20},
68 {0x20,0x20,0x20,0x20},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_sh_mask.h29 …C_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
30 …_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
31 …_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
32 …_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
33 …_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
34 …_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
35 …_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
36 …_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
37 …_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
38 …_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
[all …]
/linux/drivers/net/phy/
H A Dvitesse.c16 #define MII_VSC73XX_EXT_PAGE_1E 0x01
17 #define MII_VSC82X4_EXT_PAGE_16E 0x10
18 #define MII_VSC82X4_EXT_PAGE_17E 0x11
19 #define MII_VSC82X4_EXT_PAGE_18E 0x12
22 #define MII_VSC8244_EXT_CON1 0x17
23 #define MII_VSC8244_EXTCON1_INIT 0x0000
24 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
25 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
26 #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
27 #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_masks.h15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
[all …]

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