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Searched +full:0 +full:x18800000 (Results 1 – 18 of 18) sorted by relevance

/linux/arch/mips/pci/
H A Dpci-rc32434.c36 #define PCI_ACCESS_READ 0
53 .start = 0x50000000,
54 .end = 0x5FFFFFFF,
62 .start = 0x60000000,
63 .end = 0x6FFFFFFF,
72 .start = 0x18800000,
73 .end = 0x188FFFFF,
97 .mem_offset = 0,
98 .io_offset = 0,
105 #define PCI_ENDIAN_FLAG 0
[all …]
/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml136 enum: [0, 1]
303 reg = <0x18800000 0x800000>;
320 iommus = <&anoc2_smmu 0x1900>,
321 <&anoc2_smmu 0x1901>;
330 iommus = <&apps_smmu 0x1c02 0x1>;
340 reg = <0xa000000 0x200000>;
/linux/drivers/net/wireless/realtek/rtw89/
H A Dmac.h12 #define MAC_MEM_DUMP_PAGE_SIZE_AX 0x40000
13 #define MAC_MEM_DUMP_PAGE_SIZE_BE 0x80000
15 #define ADDR_CAM_ENT_SIZE 0x40
16 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
17 #define BSSID_CAM_ENT_SIZE 0x08
22 RTW89_DMAC_SEL = 0,
29 RTW89_FWD_DONT_CARE = 0,
45 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
57 RTW89_MAC_TAG_NUM_DEF = 0xFE
61 RTW89_MAC_LBC_TMR_8US = 0,
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dregs.h84 #define MT_RRO_TOP_BASE 0xA000
87 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8)
88 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC)
89 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8)
91 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34)
94 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38)
95 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C)
96 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40)
99 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C)
100 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60)
[all …]
/linux/arch/mips/alchemy/devboards/
H A Ddb1200.c35 #define BCSR_INT_IDE 0x0001
36 #define BCSR_INT_ETH 0x0002
37 #define BCSR_INT_PC0 0x0004
38 #define BCSR_INT_PC0STSCHG 0x0008
39 #define BCSR_INT_PC1 0x0010
40 #define BCSR_INT_PC1STSCHG 0x0020
41 #define BCSR_INT_DC 0x0040
42 #define BCSR_INT_FLASHBUSY 0x0080
43 #define BCSR_INT_PC0INSERT 0x0100
44 #define BCSR_INT_PC0EJECT 0x0200
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H A Ddb1300.c39 #define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
57 #define DB1300_ETH_PHYS_ADDR 0x19000000
58 #define DB1300_ETH_PHYS_END 0x197fffff
61 #define DB1300_IDE_PHYS_ADDR 0x18800000
66 #define DB1300_NAND_PHYS_ADDR 0x20000000
67 #define DB1300_NAND_PHYS_END 0x20000fff
71 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
72 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
85 /* wake-from-str pins 0-3 */
137 i = &db1300_dev_pins[0]; in db1300_gpio_config()
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8703b_tables.c9 { 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, },
10 { 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, },
11 { 0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636, },
12 { 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234, },
13 { 0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434, },
14 { 0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830, },
19 /* Regd: FCC -> 0, ETSI -> 2, MKK -> 1
20 * Band: 2.4G -> 0, 5G -> 1
21 * Bandwidth (bw): 20M -> 0, 40M -> 1, 80M -> 2, 160M -> 3
22 * Rate Section (rs): CCK -> 0, OFDM -> 1, HT -> 2, VHT -> 3
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8710b.c18 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
19 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
20 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
21 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
22 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
23 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
24 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
25 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
26 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66},
27 {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF},
[all …]
H A D8188f.c18 {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20},
19 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
20 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
21 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
22 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
23 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
24 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
25 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
26 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
27 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44},
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi36 #clock-cells = <0>;
43 #clock-cells = <0>;
51 #size-cells = <0>;
56 reg = <0x0 0x100>;
76 reg = <0x0 0x101>;
91 reg = <0x0 0x102>;
106 reg = <0x0 0x103>;
118 cpu4: cpu@0 {
121 reg = <0x0 0x0>;
141 reg = <0x0 0x1>;
[all …]
H A Dmsm8998.dtsi17 qcom,msm-id = <292 0x0>;
27 reg = <0x0 0x80000000 0x0 0x0>;
36 reg = <0x0 0x85800000 0x0 0x600000>;
41 reg = <0x0 0x85e00000 0x0 0x100000>;
46 reg = <0x0 0x86000000 0x0 0x200000>;
51 reg = <0x0 0x86200000 0x0 0x2d00000>;
57 reg = <0x0 0x88f00000 0x0 0x200000>;
65 reg = <0x0 0x8ab00000 0x0 0x700000>;
70 reg = <0x0 0x8b200000 0x0 0x1a00000>;
75 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
H A Dsm6350.dtsi35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
90 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da5xx.xml10 <value value="0x02" name="RB5_A8_UNORM"/>
11 <value value="0x03" name="RB5_R8_UNORM"/>
12 <value value="0x04" name="RB5_R8_SNORM"/>
13 <value value="0x05" name="RB5_R8_UINT"/>
14 <value value="0x06" name="RB5_R8_SINT"/>
15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18 <value value="0x0f" name="RB5_R8G8_UNORM"/>
19 <value value="0x10" name="RB5_R8G8_SNORM"/>
[all …]