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/linux-6.8/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.yaml73 pinctrl-0:
99 reg = <0xd4280800 0x800>;
111 reg = <0xd8000 0x1000>,
112 <0xdc000 0x100>,
113 <0x18454 0x4>;
114 interrupts = <0 25 0x4>;
117 mrvl,clk-delay-cycles = <0x1F>;
/linux-6.8/arch/arm/boot/dts/marvell/
Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/linux-6.8/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.c44 gpu->name, __builtin_return_address(0), in a6xx_idle()
121 OUT_RING(ring, 0); in a6xx_set_pagetable()
135 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); in a6xx_set_pagetable()
136 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); in a6xx_set_pagetable()
174 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); in a6xx_set_pagetable()
175 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); in a6xx_set_pagetable()
176 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); in a6xx_set_pagetable()
177 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); in a6xx_set_pagetable()
193 unsigned int i, ibs = 0; in a6xx_submit()
197 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), in a6xx_submit()
[all …]
/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_4_3_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]