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/src/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-qcom-hw.txt40 phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
51 #size-cells = <0>;
53 CPU0: cpu@0 {
56 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
72 reg = <0x0 0x100>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
85 reg = <0x0 0x200>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0x0 0x300>;
[all …]
H A Dcpufreq-qcom-hw.yaml57 - description: Frequency domain 0 register region
87 - const: dcvsh-irq-0
252 #size-cells = <0>;
254 CPU0: cpu@0 {
257 reg = <0x0 0x0>;
260 qcom,freq-domain = <&cpufreq_hw 0>;
261 clocks = <&cpufreq_hw 0>;
278 reg = <0x0 0x100>;
281 qcom,freq-domain = <&cpufreq_hw 0>;
282 clocks = <&cpufreq_hw 0>;
[all …]
/src/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm670.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]