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/linux-6.8/arch/arm64/boot/dts/freescale/
Dimx8mp-phyboard-pollux-rdk.dts25 pinctrl-0 = <&pinctrl_flexcan1_reg>;
35 pinctrl-0 = <&pinctrl_flexcan2_reg>;
45 pinctrl-0 = <&pinctrl_usb1_vbus>;
55 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
68 pinctrl-0 = <&pinctrl_eqos>;
76 #size-cells = <0>;
80 reg = <0x1>;
93 pinctrl-0 = <&pinctrl_flexcan1>;
100 pinctrl-0 = <&pinctrl_flexcan2>;
108 pinctrl-0 = <&pinctrl_i2c2>;
[all …]
Dimx8mp-skov-reva.dtsi27 pinctrl-0 = <&pinctrl_backlight>;
28 pwms = <&pwm1 0 20000 0>;
31 brightness-levels = <0 255>;
40 pinctrl-0 = <&pinctrl_gpio_led>;
42 led-0 {
125 pinctrl-0 = <&pinctrl_can2rs>;
135 pinctrl-0 = <&pinctrl_canrs>;
143 pwms = <&pwm4 0 20000 0>;
155 pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
184 pinctrl-0 = <&pinctrl_ecspi2>;
[all …]
Dimx8mp-debix-som-a-bmb-08.dts89 pinctrl-0 = <&pinctrl_reg_csi2_1v8>;
101 pinctrl-0 = <&pinctrl_reg_csi2_3v3>;
144 pinctrl-0 = <&pinctrl_eqos>;
155 #size-cells = <0>;
171 pinctrl-0 = <&pinctrl_fec>;
182 #size-cells = <0>;
198 pinctrl-0 = <&pinctrl_flexcan1>;
205 pinctrl-0 = <&pinctrl_flexcan2>;
212 pinctrl-0 = <&pinctrl_flexspi0>;
215 flash: flash@0 {
[all …]
Dimx8mp-evk.dts34 pinctrl-0 = <&pinctrl_gpio_led>;
45 reg = <0x0 0x40000000 0 0xc0000000>,
46 <0x1 0x00000000 0 0xc0000000>;
51 #clock-cells = <0>;
58 pinctrl-0 = <&pinctrl_audio_pwr_reg>;
70 pinctrl-0 = <&pinctrl_flexcan1_reg>;
81 pinctrl-0 = <&pinctrl_flexcan2_reg>;
91 pinctrl-0 = <&pinctrl_pcie0_reg>;
102 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
147 reg = <0 0x942f0000 0 0x8000>;
[all …]
Dimx8mp-venice-gw74xx.dts35 reg = <0x0 0x40000000 0 0x80000000>;
40 pinctrl-0 = <&pinctrl_usbcon1>;
56 key-0 {
66 interrupts = <0>;
101 pinctrl-0 = <&pinctrl_gpio_leds>;
103 led-0 {
121 #clock-cells = <0>;
128 pinctrl-0 = <&pinctrl_pps>;
134 pinctrl-0 = <&pinctrl_reg_usb2>;
146 pinctrl-0 = <&pinctrl_reg_can1>;
[all …]
Dimx8mp-dhcom-som.dtsi23 reg = <0x0 0x40000000 0 0x08000000>;
40 gpio = <&gpio2 19 0>; /* SD2_RESET */
43 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
83 pinctrl-0 = <&pinctrl_ecspi1>;
90 pinctrl-0 = <&pinctrl_ecspi2>;
97 pinctrl-0 = <&pinctrl_eqos_rgmii>;
105 #size-cells = <0>;
108 ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
113 pinctrl-0 = <&pinctrl_ethphy0>;
115 reg = <0>;
[all …]
Dimx8mp-msc-sm2s.dtsi25 pinctrl-0 = <&pinctrl_usb0_vbus>;
36 pinctrl-0 = <&pinctrl_usb1_vbus>;
46 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
70 lcd0_backlight: backlight-0 {
73 pinctrl-0 = <&pinctrl_lcd0_backlight>;
74 pwms = <&pwm1 0 100000 0>;
75 brightness-levels = <0 255>;
85 pinctrl-0 = <&pinctrl_lcd1_backlight>;
86 pwms = <&pwm2 0 100000 0>;
87 brightness-levels = <0 255>;
[all …]
Dimx8mm-verdin.dtsi22 brightness-levels = <0 45 63 88 119 158 203 255>;
27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
37 #clock-cells = <0>;
44 pinctrl-0 = <&pinctrl_gpio_keys>;
63 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
104 pinctrl-0 = <&pinctrl_reg_eth>;
119 pinctrl-0 = <&pinctrl_reg_usb1_en>;
131 pinctrl-0 = <&pinctrl_reg_usb2_en>;
144 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/linux-6.8/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-pcs-ufs-v2.h9 #define QPHY_V2_PCS_UFS_PHY_START 0x000
10 #define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034
13 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038
14 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c
15 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040
17 #define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
18 #define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c
19 #define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140
20 #define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148
[all …]
Dphy-qcom-qmp-pcs-ufs-v5.h11 #define QPHY_V5_PCS_UFS_PHY_START 0x000
12 #define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004
13 #define QPHY_V5_PCS_UFS_SW_RESET 0x008
14 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
15 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
16 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
17 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
18 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
19 #define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
20 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
Dphy-qcom-qmp-qserdes-txrx-v6_n4.h9 #define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_N4_TX_LANE_MODE_1 0x78
12 #define QSERDES_V6_N4_TX_LANE_MODE_2 0x7c
13 #define QSERDES_V6_N4_TX_LANE_MODE_3 0x80
15 #define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2 0x8
16 #define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2 0x18
17 #define QSERDES_V6_N4_RX_UCDR_PI_CONTROLS 0x20
18 #define QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE 0x94
19 #define QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2 0x9c
[all …]
Dphy-qcom-qmp-qserdes-com-v3.h11 #define QSERDES_V3_COM_ATB_SEL1 0x000
12 #define QSERDES_V3_COM_ATB_SEL2 0x004
13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008
14 #define QSERDES_V3_COM_BG_TIMER 0x00c
15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
18 #define QSERDES_V3_COM_SSC_PER1 0x01c
19 #define QSERDES_V3_COM_SSC_PER2 0x020
20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
[all …]
/linux-6.8/drivers/clk/mstar/
Dclk-msc313-cpupll.c17 * 0x140 -- LPF low. Seems to store one half of the clock transition
18 * 0x144 /
19 * 0x148 -- LPF high. Seems to store one half of the clock transition
20 * 0x14c /
21 * 0x150 -- vendor code says "toggle lpf enable"
22 * 0x154 -- mu?
23 * 0x15c -- lpf_update_count?
24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?
25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to
27 * 0x174 -- Seems to be the PLL lock status bit
[all …]
/linux-6.8/include/dt-bindings/clock/
Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/linux-6.8/drivers/hwmon/
Dk10temp.c38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
41 /* CPUID function 0x80000001, ebx */
43 #define CPUID_PKGTYPE_F 0x00000000
44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
47 #define REG_DCT0_CONFIG_HIGH 0x094
51 #define REG_HARDWARE_THERMAL_CONTROL 0x64
52 #define HTC_ENABLE BIT(0)
54 #define REG_REPORTED_TEMPERATURE 0xa4
56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
[all …]
/linux-6.8/drivers/devfreq/event/
Dexynos-nocp.h13 NOCP_ID_REVISION_ID = 0x04,
14 NOCP_MAIN_CTL = 0x08,
15 NOCP_CFG_CTL = 0x0C,
17 NOCP_STAT_PERIOD = 0x24,
18 NOCP_STAT_GO = 0x28,
19 NOCP_STAT_ALARM_MIN = 0x2C,
20 NOCP_STAT_ALARM_MAX = 0x30,
21 NOCP_STAT_ALARM_STATUS = 0x34,
22 NOCP_STAT_ALARM_CLR = 0x38,
24 NOCP_COUNTERS_0_SRC = 0x138,
[all …]
/linux-6.8/Documentation/devicetree/bindings/phy/
Dqcom,snps-eusb2-phy.yaml30 const: 0
76 reg = <0x88e3000 0x154>;
77 #phy-cells = <0>;
/linux-6.8/drivers/media/platform/mediatek/jpeg/
Dmtk_jpeg_enc_hw.h15 #define JPEG_ENC_INT_STATUS_DONE BIT(0)
16 #define JPEG_ENC_INT_STATUS_MASK_ALLIRQ 0x13
18 #define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
20 #define JPEG_ENC_CTRL_YUV_FORMAT_MASK 0x18
24 #define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
25 #define JPEG_ENC_RESET_BIT BIT(0)
27 #define JPEG_ENC_YUV_FORMAT_YUYV 0
32 #define JPEG_ENC_QUALITY_Q60 0x0
33 #define JPEG_ENC_QUALITY_Q80 0x1
34 #define JPEG_ENC_QUALITY_Q90 0x2
[all …]
/linux-6.8/drivers/clk/meson/
Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/linux-6.8/arch/arm/boot/dts/ti/omap/
Domap4-var-som-om44-wlan.dtsi10 pinctrl-0 = <&wl12xx_ctrl_pins>;
24 OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
25 OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
26 OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */
27 OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
33 OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */
34 OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */
35 OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */
41 OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */
42 OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */
[all …]
/linux-6.8/drivers/usb/fotg210/
Dfotg210-udc.h14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
[all …]

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