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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-nitrogen-smarc-som.dtsi25 pinctrl-0 = <&pinctrl_gpio_led>;
27 led-0 {
63 pinctrl-0 = <&pinctrl_i2c1>;
68 reg = <0x25>;
70 pinctrl-0 = <&pinctrl_pmic>;
165 pinctrl-0 = <&pinctrl_i2c6>;
171 #gpio-cells = <0x2>;
172 reg = <0x20>;
175 #interrupt-cells = <0x2>;
178 pinctrl-0 = <&pinctrl_mcp23018>;
[all …]
H A Dimx8mp-nitrogen-som.dtsi17 pinctrl-0 = <&pinctrl_rfkill_bt>;
26 pinctrl-0 = <&pinctrl_rfkill_wlan>;
52 pinctrl-0 = <&pinctrl_eqos>;
58 #size-cells = <0>;
71 pinctrl-0 = <&pinctrl_i2c1>;
79 reg = <0x25>;
81 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
82 pinctrl-0 = <&pinctrl_pmic>;
156 pinctrl-0 = <&pinctrl_i2c2>;
166 pinctrl-0 = <&pinctrl_i2c3>;
[all …]
H A Dimx8mp-phyboard-pollux-rdk.dts27 pinctrl-0 = <&pinctrl_lvds1>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
33 pwms = <&pwm3 0 50000 0>;
39 pinctrl-0 = <&pinctrl_fan>;
40 gpio-fan,speed-map = <0 0
70 pinctrl-0 = <&pinctrl_flexcan1_reg>;
80 pinctrl-0 = <&pinctrl_flexcan2_reg>;
99 pinctrl-0 = <&pinctrl_usb1_vbus>;
109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
149 #size-cells = <0>;
[all …]
H A Dimx8mp-skov-reva.dtsi28 pinctrl-0 = <&pinctrl_backlight>;
29 pwms = <&pwm1 0 20000 0>;
32 brightness-levels = <0 255>;
41 pinctrl-0 = <&pinctrl_gpio_led>;
43 led-0 {
121 pinctrl-0 = <&pinctrl_reg24v>;
131 pinctrl-0 = <&pinctrl_can2rs>;
141 pinctrl-0 = <&pinctrl_canrs>;
149 pwms = <&pwm4 0 20000 0>;
161 pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
[all …]
H A Dimx8mp-venice-gw82xx.dtsi20 pinctrl-0 = <&pinctrl_gpio_leds>;
22 led-0 {
40 #clock-cells = <0>;
47 pinctrl-0 = <&pinctrl_pps>;
54 pinctrl-0 = <&pinctrl_reg_usb2_en>;
65 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
78 pinctrl-0 = <&pinctrl_spi2>;
85 tpm@0 {
87 reg = <0x0>;
94 pinctrl-0 = <&pinctrl_can1>;
[all …]
H A Dimx8mp-debix-som-a-bmb-08.dts89 pinctrl-0 = <&pinctrl_reg_csi2_1v8>;
101 pinctrl-0 = <&pinctrl_reg_csi2_3v3>;
144 pinctrl-0 = <&pinctrl_eqos>;
154 #size-cells = <0>;
170 pinctrl-0 = <&pinctrl_fec>;
181 #size-cells = <0>;
197 pinctrl-0 = <&pinctrl_flexcan1>;
204 pinctrl-0 = <&pinctrl_flexcan2>;
211 pinctrl-0 = <&pinctrl_flexspi0>;
214 flash: flash@0 {
[all …]
H A Dimx8mp-evk.dts21 pwms = <&pwm2 0 100000 0>;
22 brightness-levels = <0 100>;
44 pinctrl-0 = <&pinctrl_gpio_led>;
55 reg = <0x0 0x40000000 0 0xc0000000>,
56 <0x1 0x00000000 0 0xc0000000>;
73 #clock-cells = <0>;
98 pinctrl-0 = <&pinctrl_audio_pwr_reg>;
110 pinctrl-0 = <&pinctrl_flexcan1_reg>;
121 pinctrl-0 = <&pinctrl_flexcan2_reg>;
131 pinctrl-0 = <&pinctrl_pcie0_reg>;
[all …]
H A Dimx8mp-aristainetos3a-som-v1.dtsi24 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
42 pinctrl-0 = <&pinctrl_gpio_led>;
44 led-0 {
47 function-enumerator = <0>;
56 pinctrl-0 = <&pinctrl_lvds_bklt_en>;
57 pwms = <&pwm2 0 50000 0>;
59 brightness-levels = <0 100>;
68 reg = <0x0 0x40000000 0 0x08000000>;
73 #clock-cells = <0>;
80 pinctrl-0 = <&pinctrl_flexcan1_reg>;
[all …]
H A Dimx8mp-venice-gw74xx.dts38 reg = <0x0 0x40000000 0 0x80000000>;
43 pinctrl-0 = <&pinctrl_usbcon1>;
59 key-0 {
69 interrupts = <0>;
104 pinctrl-0 = <&pinctrl_gpio_leds>;
106 led-0 {
124 #clock-cells = <0>;
131 pinctrl-0 = <&pinctrl_pps>;
137 pinctrl-0 = <&pinctrl_reg_usb2>;
149 pinctrl-0 = <&pinctrl_reg_can1>;
[all …]
H A Dimx8mp-dhcom-som.dtsi23 reg = <0x0 0x40000000 0 0x08000000>;
40 gpio = <&gpio2 19 0>; /* SD2_RESET */
43 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
88 pinctrl-0 = <&pinctrl_ecspi1>;
95 pinctrl-0 = <&pinctrl_ecspi2>;
102 pinctrl-0 = <&pinctrl_eqos_rgmii>;
110 #size-cells = <0>;
118 pinctrl-0 = <&pinctrl_ethphy0>;
133 micrel,led-mode = <0>;
134 pinctrl-0 = <&pinctrl_ethphy0>;
[all …]
H A Dimx8mp-phycore-fpsc.dtsi20 reg = <0x0 0x40000000 0x0 0x80000000>;
26 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
61 pinctrl-0 = <&pinctrl_ecspi1>;
66 pinctrl-0 = <&pinctrl_ecspi2>;
71 pinctrl-0 = <&pinctrl_ecspi3>;
77 pinctrl-0 = <&pinctrl_eqos>;
84 pinctrl-0 = <&pinctrl_fec>;
91 #size-cells = <0>;
93 ethphy0: ethernet-phy@0 {
95 reg = <0>;
[all …]
H A Dimx8mm-verdin.dtsi24 #clock-cells = <0>;
31 pinctrl-0 = <&pinctrl_gpio_keys>;
50 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
84 pinctrl-0 = <&pinctrl_reg_eth>;
115 pinctrl-0 = <&pinctrl_reg_usb1_en>;
127 pinctrl-0 = <&pinctrl_reg_usb2_en>;
140 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
150 pinctrl-0 = <&pinctrl_usdhc2_vsel>;
154 states = <1800000 0x1>,
155 <3300000 0x0>;
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-pcs-ufs-v2.h9 #define QPHY_V2_PCS_UFS_PHY_START 0x000
10 #define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034
13 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038
14 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c
15 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040
17 #define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
18 #define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c
19 #define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140
20 #define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148
[all …]
H A Dphy-qcom-qmp-pcs-ufs-v5.h11 #define QPHY_V5_PCS_UFS_PHY_START 0x000
12 #define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004
13 #define QPHY_V5_PCS_UFS_SW_RESET 0x008
14 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
15 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
16 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
17 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
18 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
19 #define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
20 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
H A Dphy-qcom-qmp-qserdes-com-v3.h11 #define QSERDES_V3_COM_ATB_SEL1 0x000
12 #define QSERDES_V3_COM_ATB_SEL2 0x004
13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008
14 #define QSERDES_V3_COM_BG_TIMER 0x00c
15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
18 #define QSERDES_V3_COM_SSC_PER1 0x01c
19 #define QSERDES_V3_COM_SSC_PER2 0x020
20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
[all …]
/linux/drivers/clk/mstar/
H A Dclk-msc313-cpupll.c17 * 0x140 -- LPF low. Seems to store one half of the clock transition
18 * 0x144 /
19 * 0x148 -- LPF high. Seems to store one half of the clock transition
20 * 0x14c /
21 * 0x150 -- vendor code says "toggle lpf enable"
22 * 0x154 -- mu?
23 * 0x15c -- lpf_update_count?
24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?
25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to
27 * 0x174 -- Seems to be the PLL lock status bit
[all …]
/linux/include/dt-bindings/clock/
H A Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dsophgo,cv1800b-dmamux.yaml48 reg = <0x154 0x8>, <0x298 0x4>;
/linux/drivers/devfreq/event/
H A Dexynos-nocp.h13 NOCP_ID_REVISION_ID = 0x04,
14 NOCP_MAIN_CTL = 0x08,
15 NOCP_CFG_CTL = 0x0C,
17 NOCP_STAT_PERIOD = 0x24,
18 NOCP_STAT_GO = 0x28,
19 NOCP_STAT_ALARM_MIN = 0x2C,
20 NOCP_STAT_ALARM_MAX = 0x30,
21 NOCP_STAT_ALARM_STATUS = 0x34,
22 NOCP_STAT_ALARM_CLR = 0x38,
24 NOCP_COUNTERS_0_SRC = 0x138,
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,snps-eusb2-phy.yaml32 const: 0
78 reg = <0x88e3000 0x154>;
79 #phy-cells = <0>;
/linux/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_enc_hw.h15 #define JPEG_ENC_INT_STATUS_DONE BIT(0)
16 #define JPEG_ENC_INT_STATUS_MASK_ALLIRQ 0x13
18 #define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
20 #define JPEG_ENC_CTRL_YUV_FORMAT_MASK 0x18
24 #define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
25 #define JPEG_ENC_RESET_BIT BIT(0)
27 #define JPEG_ENC_YUV_FORMAT_YUYV 0
32 #define JPEG_ENC_QUALITY_Q60 0x0
33 #define JPEG_ENC_QUALITY_Q80 0x1
34 #define JPEG_ENC_QUALITY_Q90 0x2
[all …]
/linux/drivers/hwmon/
H A Dk10temp.c38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
41 /* CPUID function 0x80000001, ebx */
43 #define CPUID_PKGTYPE_F 0x00000000
44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
47 #define REG_DCT0_CONFIG_HIGH 0x094
51 #define REG_HARDWARE_THERMAL_CONTROL 0x64
52 #define HTC_ENABLE BIT(0)
54 #define REG_REPORTED_TEMPERATURE 0xa4
56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
[all …]

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