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/linux-5.10/drivers/bus/
Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/linux-5.10/arch/sparc/include/asm/
Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/linux-5.10/arch/arm/boot/dts/
Dstm32mp153.dtsi28 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
35 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
41 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
48 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
35 #clock-cells = <0>;
39 reg = <0x0d50>;
44 #clock-cells = <0>;
48 reg = <0x0b00>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
[all …]
Ddm816x-clocks.dtsi7 reg = <0x400 0x40>;
23 reg = <0x440 0x30>;
35 reg = <0x470 0x30>;
46 reg = <0x4a0 0x30>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
83 /* 0x48180000 */
86 #clock-cells = <0>;
[all …]
Ddm814x-clocks.dtsi12 reg = <0x40 0x40>;
24 reg = <0x80 0x30>;
35 reg = <0xb0 0x30>;
46 reg = <0xe0 0x30>;
57 reg = <0x110 0x30>;
68 reg = <0x140 0x30>;
79 reg = <0x170 0x30>;
90 reg = <0x1a0 0x30>;
101 reg = <0x1d0 0x30>;
112 reg = <0x200 0x30>;
[all …]
/linux-5.10/arch/m68k/include/asm/
Dcontregs.h15 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
16 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
17 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
18 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
19 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
20 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
21 #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
22 #define AC_SYNC_ERR 0x60000000 /* c fault type */
23 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
24 #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
[all …]
/linux-5.10/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-qcom-hw.txt40 phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
51 #size-cells = <0>;
53 CPU0: cpu@0 {
56 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
72 reg = <0x0 0x100>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
85 reg = <0x0 0x200>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0x0 0x300>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-sdram-controller.txt20 reg = <0x1400 0x500>;
/linux-5.10/drivers/net/wireless/intersil/prism54/
Dislpci_eth.h13 __le16 unk0; /* = 0x0000 */
14 __le16 length; /* = 0x1400 */
34 #define P80211CAPTURE_VERSION 0x80211001
/linux-5.10/arch/arm/mach-omap2/
Domap34xx.h17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
Dcm81xx.h21 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
22 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
23 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
24 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
27 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
28 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
29 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
32 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
33 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
34 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dqcom,osm-l3.yaml54 #define RPMH_CXO_CLK 0
58 reg = <0x17d41000 0x1400>;
/linux-5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Dpar_io.txt18 #size-cells = <0>;
41 reg = <0x1400 0x18>;
49 reg = <0x1460 0x18>;
/linux-5.10/arch/s390/include/asm/
Dlowcore.h21 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
22 __u32 ipl_parmblock_ptr; /* 0x0014 */
23 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
24 __u32 ext_params; /* 0x0080 */
25 __u16 ext_cpu_addr; /* 0x0084 */
26 __u16 ext_int_code; /* 0x0086 */
27 __u16 svc_ilc; /* 0x0088 */
28 __u16 svc_code; /* 0x008a */
29 __u16 pgm_ilc; /* 0x008c */
30 __u16 pgm_code; /* 0x008e */
[all …]
/linux-5.10/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_reg.c33 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
34 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
35 {0x1200, 0x12E0} } },
36 {NIX_TXSCH_LVL_TL3, 3, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
37 {0x1610, 0x1618} } },
38 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x1768} } },
39 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
48 if (reg & 0x07) in rvu_check_valid_reg()
65 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/linux-5.10/drivers/mfd/
Dtimberdale.h23 #define TIMB_REV_MAJOR 0x00
24 #define TIMB_REV_MINOR 0x04
25 #define TIMB_HW_CONFIG 0x08
26 #define TIMB_SW_RST 0x40
29 #define TIMB_HW_CONFIG_SPI_8BIT 0x80
31 #define TIMB_HW_VER_MASK 0x0f
32 #define TIMB_HW_VER0 0x00
33 #define TIMB_HW_VER1 0x01
34 #define TIMB_HW_VER2 0x02
35 #define TIMB_HW_VER3 0x03
[all …]
/linux-5.10/drivers/edac/
Dmv64x60_edac.h15 #define MV64x60_REVISION " Ver: 2.0.0"
25 #define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */
26 #define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */
27 #define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */
28 #define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */
29 #define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */
30 #define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */
31 #define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */
33 #define MV64x60_CPU_CAUSE_MASK 0x07ffffff
36 #define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */
[all …]
/linux-5.10/drivers/regulator/
Dqcom_spmi-regulator.c24 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
32 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/linux-5.10/drivers/media/usb/gspca/stv06xx/
Dstv06xx.c36 u8 len = (i2c_data > 0xff) ? 2 : 1; in stv06xx_write_bridge()
38 buf[0] = i2c_data & 0xff; in stv06xx_write_bridge()
39 buf[1] = (i2c_data >> 8) & 0xff; in stv06xx_write_bridge()
41 err = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), in stv06xx_write_bridge()
42 0x04, 0x40, address, 0, buf, len, in stv06xx_write_bridge()
45 gspca_dbg(gspca_dev, D_CONF, "Written 0x%x to address 0x%x, status: %d\n", in stv06xx_write_bridge()
48 return (err < 0) ? err : 0; in stv06xx_write_bridge()
58 err = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), in stv06xx_read_bridge()
59 0x04, 0xc0, address, 0, buf, 1, in stv06xx_read_bridge()
62 *i2c_data = buf[0]; in stv06xx_read_bridge()
[all …]
/linux-5.10/include/video/
Dneomagic.h11 #define NEO_BS0_BLT_BUSY 0x00000001
12 #define NEO_BS0_FIFO_AVAIL 0x00000002
13 #define NEO_BS0_FIFO_PEND 0x00000004
15 #define NEO_BC0_DST_Y_DEC 0x00000001
16 #define NEO_BC0_X_DEC 0x00000002
17 #define NEO_BC0_SRC_TRANS 0x00000004
18 #define NEO_BC0_SRC_IS_FG 0x00000008
19 #define NEO_BC0_SRC_Y_DEC 0x00000010
20 #define NEO_BC0_FILL_PAT 0x00000020
21 #define NEO_BC0_SRC_MONO 0x00000040
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv50.c32 /* 0x01: no bank swizzle in nv50_mmu_kind()
33 * 0x02: bank swizzled in nv50_mmu_kind()
34 * 0x7f: invalid in nv50_mmu_kind()
36 * 0x01/0x02 are values understood by the VRAM allocator, in nv50_mmu_kind()
42 0x01, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x00 */ in nv50_mmu_kind()
43 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, in nv50_mmu_kind()
44 0x01, 0x01, 0x01, 0x01, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x10 */ in nv50_mmu_kind()
45 0x02, 0x02, 0x02, 0x02, 0x7f, 0x7f, 0x7f, 0x7f, in nv50_mmu_kind()
46 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, /* 0x20 */ in nv50_mmu_kind()
47 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7f, in nv50_mmu_kind()
[all …]
/linux-5.10/lib/
Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/linux-5.10/drivers/net/ethernet/ezchip/
Dnps_enet.h10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
[all …]
/linux-5.10/sound/pci/cs46xx/
Ddsp_spos.h18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
32 WIDE_FOR_BEGIN_LOOP = 0x20,
35 WIDE_COND_GOTO_ADDR = 0x30,
[all …]

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