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/qemu/hw/misc/
H A Dallwinner-sramc.c37 REG_SRAM_CTL1_CFG = 0x04, /* SRAM Control register 1 */
38 REG_SRAM_VER = 0x24, /* SRAM Version register */
39 REG_SRAM_R40_SOFT_ENTRY_REG0 = 0xbc,
45 #define SRAM_VERSION_SUN8I_R40 0x1701
52 uint64_t val = 0; in allwinner_sramc_read()
69 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", in allwinner_sramc_read()
71 return 0; in allwinner_sramc_read()
98 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", in allwinner_sramc_write()
133 s->sram_ctl1 = 0x1300; in allwinner_sramc_reset()
H A Dexynos4210_pmu.c35 #define DEBUG_PMU 0
39 #define DEBUG_PMU_EXTEND 0
46 } while (0)
52 } while (0)
54 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
58 #define PRINT_DEBUG(fmt, args...) do {} while (0)
59 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
65 #define OM_STAT 0x0000 /* OM status register */
66 #define RTC_CLKO_SEL 0x000C /* Controls RTCCLKOUT */
67 #define GNSS_RTC_OUT_CTRL 0x0010 /* Controls GNSS_RTC_OUT */
[all …]
/qemu/docs/specs/
H A Dppc-spapr-xive.rst199 - ``0x0000 .. 0x0FFF`` 4K CPU IPIs (only used under XIVE)
200 - ``0x1000 .. 0x1000`` 1 EPOW
201 - ``0x1001 .. 0x1001`` 1 HOTPLUG
202 - ``0x1002 .. 0x10FF`` unused
203 - ``0x1100 .. 0x11FF`` 256 VIO devices
204 - ``0x1200 .. 0x127F`` 32x4 LSIs for PHB devices
205 - ``0x1280 .. 0x12FF`` unused
206 - ``0x1300 .. 0x1FFF`` PHB MSIs (dynamically allocated)
238 00000000 MSI -- 00000010 0/6 380/16384 @1fe3e0000 ^1 [ 80000010 ... ]
246 00001000 MSI -- 00000012 0/6 380/16384 @1fe3e0000 ^1 [ 80000010 ... ]
[all …]
/qemu/target/s390x/
H A Ds390x-internal.h19 uint32_t ccw1[2]; /* 0x000 */
20 uint32_t ccw2[4]; /* 0x008 */
21 uint8_t pad1[0x80 - 0x18]; /* 0x018 */
22 uint32_t ext_params; /* 0x080 */
23 uint16_t cpu_addr; /* 0x084 */
24 uint16_t ext_int_code; /* 0x086 */
25 uint16_t svc_ilen; /* 0x088 */
26 uint16_t svc_code; /* 0x08a */
27 uint16_t pgm_ilen; /* 0x08c */
28 uint16_t pgm_code; /* 0x08e */
[all …]
/qemu/include/hw/misc/
H A Dbcm2835_cprman_internals.h32 REG32(CM_PLLA, 0x104)
33 FIELD(CM_PLLA, LOADDSI0, 0, 1)
42 REG32(CM_PLLC, 0x108)
43 FIELD(CM_PLLC, LOADCORE0, 0, 1)
51 REG32(CM_PLLD, 0x10c)
52 FIELD(CM_PLLD, LOADDSI0, 0, 1)
60 REG32(CM_PLLH, 0x110)
61 FIELD(CM_PLLH, LOADPIX, 0, 1)
64 REG32(CM_PLLB, 0x170)
65 FIELD(CM_PLLB, LOADARM, 0, 1)
[all …]
/qemu/hw/smbios/
H A Dsmbios.c48 static int smbios_type4_count = 0;
68 * 0 which counts as unknown (SMBIOS 3.1.0/Table 21). Set the
82 .processor_id = 0,
83 .processor_family = 0x01, /* Other */
509 #define SMBIOS_21_MAX_TABLES_LEN 0xffff
546 #define T0_BASE 0x000
547 #define T1_BASE 0x100
548 #define T2_BASE 0x200
549 #define T3_BASE 0x300
550 #define T4_BASE 0x400
[all …]
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc26 C(0x1a00, AR, RR_a, Z, r1, r2, new, r1_32, add, adds32)
27 C(0xb9f8, ARK, RRF_a, DO, r2, r3, new, r1_32, add, adds32)
28 C(0x5a00, A, RX_a, Z, r1, m2_32s, new, r1_32, add, adds32)
29 C(0xe35a, AY, RXY_a, LD, r1, m2_32s, new, r1_32, add, adds32)
30 C(0xb908, AGR, RRE, Z, r1, r2, r1, 0, add, adds64)
31 C(0xb918, AGFR, RRE, Z, r1, r2_32s, r1, 0, add, adds64)
32 C(0xb9e8, AGRK, RRF_a, DO, r2, r3, r1, 0, add, adds64)
33 C(0xe308, AG, RXY_a, Z, r1, m2_64, r1, 0, add, adds64)
34 C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64)
35 F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP)
[all …]