Searched +full:0 +full:x1000a000 (Results 1 – 7 of 7) sorted by relevance
40 reg = <0x10027000 0x800>;46 reg = <0x1000a000 0x1000>;
43 reg = <0x10027000 0x1000>;50 reg = <0x1000a000 0x1000>;
9 #define IMX1_UART1_BASE_ADDR 0x0020600010 #define IMX1_UART2_BASE_ADDR 0x0020700014 #define IMX21_UART1_BASE_ADDR 0x1000a00015 #define IMX21_UART2_BASE_ADDR 0x1000b00016 #define IMX21_UART3_BASE_ADDR 0x1000c00017 #define IMX21_UART4_BASE_ADDR 0x1000d00021 #define IMX25_UART1_BASE_ADDR 0x43f9000022 #define IMX25_UART2_BASE_ADDR 0x43f9400023 #define IMX25_UART3_BASE_ADDR 0x5000c00024 #define IMX25_UART4_BASE_ADDR 0x50008000[all …]
43 /* 128 MiB memory @ 0x0 */44 reg = <0x00000000 0x08000000>;48 vmmc: fixedregulator@0 {57 #clock-cells = <0>;63 #clock-cells = <0>;71 #clock-cells = <0>;79 #clock-cells = <0>;87 #clock-cells = <0>;95 #clock-cells = <0>;103 #clock-cells = <0>;[all …]
44 /* 128 MiB memory @ 0x0 */45 reg = <0x00000000 0x08000000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;86 #clock-cells = <0>;94 #clock-cells = <0>;102 #clock-cells = <0>;110 #clock-cells = <0>;118 #clock-cells = <0>;[all …]
47 reg = <0x10040000 0x1000>;53 #clock-cells = <0>;59 #size-cells = <0>;62 cpu: cpu@0 {64 reg = <0>;88 reg = <0x10000000 0x20000>;93 reg = <0x10001000 0x1000>;104 reg = <0x10002000 0x1000>;111 reg = <0x10003000 0x1000>;120 reg = <0x10004000 0x1000>;[all …]
45 * The PB11MPCore has 512 MiB memory @ 0x7000000046 * and the first 256 are also remapped @ 0x0000000048 reg = <0x70000000 0x20000000>;53 #size-cells = <0>;56 MP11_0: cpu@0 {59 reg = <0>;91 reg = <0x1f001000 0x1000>,92 <0x1f000100 0x100>;97 reg = <0x1f002000 0x1000>;99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,[all …]