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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra194-axi2apb.yaml14 pattern: "^axi2apb@([0-9a-f]+)$"
34 reg = <0x02390000 0x1000>,
35 <0x023a0000 0x1000>,
36 <0x023b0000 0x1000>,
37 <0x023c0000 0x1000>,
38 <0x023d0000 0x1000>,
39 <0x023e0000 0x1000>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-1.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x820 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
56 reg = <0x82000 0x1000>;
60 cell-index = <0x3>;
[all …]
H A Dqoriq-fman3-0.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x800 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
[all …]
H A Dqoriq-fman-0.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x40 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
[all …]
H A Dqoriq-fman-1.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x60 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
56 reg = <0x81000 0x1000>;
60 cell-index = <0x2>;
[all …]
/linux/arch/arm64/boot/dts/nuvoton/
H A Dnuvoton-common-npcm8xx.dtsi22 reg = <0x0 0xf0800000 0x0 0x1000>;
27 reg = <0x0 0xdfff9000 0x0 0x1000>,
28 <0x0 0xdfffa000 0x0 0x2000>,
29 <0x0 0xdfffc000 0x0 0x2000>,
30 <0x0 0xdfffe000 0x0 0x2000>;
34 #address-cells = <0>;
47 reg = <0x0 0xf0801000 0x0 0x78>;
55 reg = <0x0 0xf0801000 0x0 0x1000>;
63 ranges = <0x0 0x0 0xf0000000 0x00300000>,
64 <0xfff00000 0x0 0xfff00000 0x00016000>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dpxa168.dtsi32 reg = <0xd4200000 0x00200000>;
39 reg = <0xd4282000 0x1000>;
49 reg = <0xd4000000 0x00200000>;
54 reg = <0xd4014000 0x100>;
62 reg = <0xd4017000 0x1000>;
72 reg = <0xd4018000 0x1000>;
82 reg = <0xd4026000 0x1000>;
94 reg = <0xd4019000 0x1000>;
106 reg = <0xd4019000 0x4>;
110 reg = <0xd4019004 0x4>;
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi31 bootscr-address = /bits/ 64 <0x20000000>;
37 #size-cells = <0>;
39 cpu0: cpu@0 {
45 reg = <0x0>;
55 reg = <0x1>;
66 reg = <0x2>;
77 reg = <0x3>;
92 CPU_SLEEP_0: cpu-sleep-0 {
94 arm,psci-suspend-param = <0x40000000>;
135 reg = <0x0 0x3ed00000 0x0 0x40000>;
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8226.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
47 reg = <0>;
110 memory@0 {
112 reg = <0x0 0x0>;
161 mboxes = <&apcs 0>;
213 reg = <0x3000000 0x100000>;
218 reg = <0x08000000 0x5100000>;
[all …]
H A Dqcom-msm8660.dtsi18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0>;
45 reg = <0x0 0x0>;
56 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
86 reg = < 0x02080000 0x1000 >,
87 < 0x02081000 0x1000 >;
92 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
[all …]
H A Dqcom-mdm9615.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
31 reg = <0>;
45 #clock-cells = <0>;
66 reg = <0x02040000 0x1000>;
67 arm,data-latency = <2 2 0>;
76 reg = <0x02000000 0x1000>,
77 <0x02002000 0x1000>;
86 reg = <0x0200a000 0x100>;
88 cpu-offset = <0x80000>;
[all …]
H A Dqcom-msm8974.dtsi23 #clock-cells = <0>;
29 #clock-cells = <0>;
36 #size-cells = <0>;
39 cpu0: cpu@0 {
43 reg = <0>;
109 memory@0 {
111 reg = <0x0 0x0>;
136 mboxes = <&apcs 0>;
159 reg = <0x08000000 0x5100000>;
164 reg = <0x0d100000 0x100000>;
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7870.dtsi32 #size-cells = <0>;
66 cpu0: cpu@0 {
69 reg = <0x0>;
76 reg = <0x1>;
83 reg = <0x2>;
90 reg = <0x3>;
97 reg = <0x100>;
104 reg = <0x101>;
111 reg = <0x102>;
118 reg = <0x103>;
[all …]
H A Dexynos9810.dtsi32 #size-cells = <0>;
66 cpu0: cpu@0 {
69 reg = <0x0>;
76 reg = <0x1>;
83 reg = <0x2>;
90 reg = <0x3>;
97 reg = <0x100>;
104 reg = <0x101>;
111 reg = <0x102>;
118 reg = <0x103>;
[all …]
H A Dexynos8895.dtsi31 #size-cells = <0>;
65 cpu4: cpu@0 {
68 reg = <0x0>;
75 reg = <0x1>;
82 reg = <0x2>;
89 reg = <0x3>;
96 reg = <0x100>;
103 reg = <0x101>;
110 reg = <0x102>;
117 reg = <0x103>;
[all …]
H A Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dmediatek-mdp.txt35 reg = <0 0x14001000 0 0x1000>;
45 reg = <0 0x14002000 0 0x1000>;
54 reg = <0 0x14003000 0 0x1000>;
61 reg = <0 0x14004000 0 0x1000>;
68 reg = <0 0x14005000 0 0x1000>;
75 reg = <0 0x14006000 0 0x1000>;
83 reg = <0 0x14007000 0 0x1000>;
91 reg = <0 0x14008000 0 0x1000>;
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmgk104.c41 { SPT, 15, 8, 0x1000, &gf100_vmm_pgt },
42 { PGD, 13, 8, 0x1000, &gf100_vmm_pgd },
48 { LPT, 10, 8, 0x1000, &gk104_vmm_lpt },
49 { PGD, 13, 8, 0x1000, &gf100_vmm_pgd },
55 { SPT, 14, 8, 0x1000, &gf100_vmm_pgt },
56 { PGD, 14, 8, 0x1000, &gf100_vmm_pgd },
62 { LPT, 10, 8, 0x1000, &gk104_vmm_lpt },
63 { PGD, 14, 8, 0x1000, &gf100_vmm_pgd },
76 { 17, &gk104_vmm_desc_17_17[0], NVKM_VMM_PAGE_xVxC },
77 { 12, &gk104_vmm_desc_17_12[0], NVKM_VMM_PAGE_xVHx },
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
/linux/arch/arm64/boot/dts/realtek/
H A Drtd139x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
25 reg = <0x2f000 0x1000>;
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
46 #clock-cells = <0>;
50 soc@0 {
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
59 reg = <0x98000000 0x200000>;
[all …]
/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
96 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
[all …]

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