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/linux-5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt6765.c14 * iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800,
15 * iocfg[3]:0x10002A00, iocfg[4]:0x10002000, iocfg[5]:0x10002200,
16 * iocfg[6]:0x10002500, iocfg[7]:0x10002600.
22 _x_bits, 32, 0)
29 PIN_FIELD(0, 202, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 202, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 202, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 202, 0x100, 0x10, 0, 1),
45 PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1),
46 PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1),
[all …]
Dpinctrl-mt6779.c13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
21 32, 0)
28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
[all …]
Dpinctrl-mt8192.c13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000,
14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000,
15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000,
16 * iocfg_tl:0x11F30000
22 32, 0)
29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
[all …]
Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
Dpinctrl-mt7623.c13 #define PIN_BOND_REG0 0xb10
14 #define PIN_BOND_REG1 0xf20
15 #define PIN_BOND_REG2 0xef0
16 #define BOND_PCIE_CLR (0x77 << 3)
17 #define BOND_I2S_CLR 0x3
18 #define BOND_MSDC0E_CLR 0x1
21 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
25 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
26 _x_bits, 16, 0)
29 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
[all …]
/linux-5.10/fs/unicode/
Dutf8data.h_shipped6 static const unsigned int utf8vers = 0xc0100;
9 0,
10 0x10100,
11 0x20000,
12 0x20100,
13 0x30000,
14 0x30100,
15 0x30200,
16 0x40000,
17 0x40100,
[all …]
/linux-5.10/include/linux/mlx5/
Dmlx5_ifc.h38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
[all …]
/linux-5.10/drivers/media/usb/gspca/
Dsonixj.c64 #define BRIDGE_SN9C102P 0
94 #define F_PDN_INV 0x01 /* inverse pin S_PWR_DN / sn_xxx tables */
95 #define F_ILLUM 0x02 /* presence of illuminator */
98 /* register 0x01 */
99 #define S_PWR_DN 0x01 /* sensor power down */
100 #define S_PDN_INV 0x02 /* inverse pin S_PWR_DN */
101 #define V_TX_EN 0x04 /* video transfer enable */
102 #define LED 0x08 /* output to pin LED */
103 #define SCL_SEL_OD 0x20 /* open-drain mode */
104 #define SYS_SEL_48M 0x40 /* system clock 0: 24MHz, 1: 48MHz */
[all …]
Dnw80x.c159 * - 3rd byte: data length (=0 for end of sequence)
162 #define I2C0 0xff
165 0x04, 0x05, 0x01, 0x61,
166 0x04, 0x04, 0x01, 0x01,
167 0x04, 0x06, 0x01, 0x04,
168 0x04, 0x04, 0x03, 0x00, 0x00, 0x00,
169 0x05, 0x05, 0x01, 0x00,
170 0, 0, 0
173 0x04, 0x06, 0x01, 0xc0,
174 0x00, 0x00, 0x40, 0x10, 0x43, 0x00, 0xb4, 0x01, 0x10, 0x00, 0x4f,
[all …]
/linux-5.10/lib/fonts/
Dfont_6x8.c7 { 0, 0, FONTDATAMAX, 0 }, {
8 /* 0 0x00 '^@' */
9 0x00, /* 000000 */
10 0x00, /* 000000 */
11 0x00, /* 000000 */
12 0x00, /* 000000 */
13 0x00, /* 000000 */
14 0x00, /* 000000 */
15 0x00, /* 000000 */
16 0x00, /* 000000 */
[all …]
Dfont_6x10.c7 { 0, 0, FONTDATAMAX, 0 }, {
8 /* 0 0x00 '^@' */
9 0x00, /* 00000000 */
10 0x00, /* 00000000 */
11 0x00, /* 00000000 */
12 0x00, /* 00000000 */
13 0x00, /* 00000000 */
14 0x00, /* 00000000 */
15 0x00, /* 00000000 */
16 0x00, /* 00000000 */
[all …]
Dfont_6x11.c13 { 0, 0, FONTDATAMAX, 0 }, {
14 /* 0 0x00 '^@' */
15 0x00, /* 00000000 */
16 0x00, /* 00000000 */
17 0x00, /* 00000000 */
18 0x00, /* 00000000 */
19 0x00, /* 00000000 */
20 0x00, /* 00000000 */
21 0x00, /* 00000000 */
22 0x00, /* 00000000 */
[all …]
/linux-5.10/arch/x86/crypto/
Daegis128-aesni-asm.S30 .byte 0x00, 0x01, 0x01, 0x02, 0x03, 0x05, 0x08, 0x0d
31 .byte 0x15, 0x22, 0x37, 0x59, 0x90, 0xe9, 0x79, 0x62
33 .byte 0xdb, 0x3d, 0x18, 0x55, 0x6d, 0xc2, 0x2f, 0xf1
34 .byte 0x20, 0x11, 0x31, 0x42, 0x73, 0xb5, 0x28, 0xdd
39 .byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
40 .byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
47 * STATE[0-4] - input state
49 * STATE[0-4] - output state (shifted positions)
79 and $0x1, %r8
83 and $0x1E, %r8
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
Ddce_11_2_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
Ddce_10_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_0_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/linux-5.10/arch/arm/boot/dts/
Dam335x-pocketbeagle.dts22 pinctrl-0 = <&usr_leds_pins>;
121 "[USR LED 0]",
210 pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio
215 /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */
220 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
221 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
224 /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */
229 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
230 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
233 /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */
[all …]
/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/steering/
Dmlx5_ifc_dr.h8 MLX5DR_ACTION_MDFY_HW_FLD_L2_0 = 0,
35 MLX5DR_ACTION_MDFY_HW_OP_COPY = 0x1,
36 MLX5DR_ACTION_MDFY_HW_OP_SET = 0x2,
37 MLX5DR_ACTION_MDFY_HW_OP_ADD = 0x3,
41 MLX5DR_ACTION_MDFY_HW_HDR_L3_NONE = 0x0,
42 MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4 = 0x1,
43 MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6 = 0x2,
47 MLX5DR_ACTION_MDFY_HW_HDR_L4_NONE = 0x0,
48 MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP = 0x1,
49 MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP = 0x2,
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_0_sh_mask.h27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
37 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
38 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
Ddcn_3_0_0_sh_mask.h7 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
8 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
9 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
10 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
12 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
13 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
14 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
15 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
17 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
18 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]

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