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/linux/sound/soc/codecs/
H A Dmt6359.h11 #define MT6359_TOP0_ID 0x0
12 #define MT6359_SMT_CON1 0x32
13 #define MT6359_DRV_CON2 0x3c
14 #define MT6359_DRV_CON3 0x3e
15 #define MT6359_DRV_CON4 0x40
16 #define MT6359_TOP_CKPDN_CON0 0x10c
17 #define MT6359_TOP_CKPDN_CON0_SET 0x10e
18 #define MT6359_TOP_CKPDN_CON0_CLR 0x110
19 #define MT6359_AUXADC_RQST0 0x1108
20 #define MT6359_AUXADC_CON10 0x11a
[all...]
H A Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
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H A Drt5616.h13 #define RT5616_RESET 0x00
14 #define RT5616_VERSION_ID 0xfd
15 #define RT5616_VENDOR_ID 0xfe
16 #define RT5616_DEVICE_ID 0xff
18 #define RT5616_HP_VOL 0x02
19 #define RT5616_LOUT_CTRL1 0x03
20 #define RT5616_LOUT_CTRL2 0x05
22 #define RT5616_IN1_IN2 0x0d
23 #define RT5616_INL1_INR1_VOL 0x0f
25 #define RT5616_DAC1_DIG_VOL 0x1
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H A Drt5651.h15 #define RT5651_RESET 0x00
16 #define RT5651_VERSION_ID 0xfd
17 #define RT5651_VENDOR_ID 0xfe
18 #define RT5651_DEVICE_ID 0xff
20 #define RT5651_HP_VOL 0x02
21 #define RT5651_LOUT_CTRL1 0x03
22 #define RT5651_LOUT_CTRL2 0x05
24 #define RT5651_IN1_IN2 0x0d
25 #define RT5651_IN3 0x0e
26 #define RT5651_INL1_INR1_VOL 0x0
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H A Drt5645.h13 #define RT5645_RESET 0x00
14 #define RT5645_VENDOR_ID 0xfd
15 #define RT5645_VENDOR_ID1 0xfe
16 #define RT5645_VENDOR_ID2 0xff
18 #define RT5645_SPK_VOL 0x01
19 #define RT5645_HP_VOL 0x02
20 #define RT5645_LOUT1 0x03
21 #define RT5645_LOUT_CTRL 0x05
23 #define RT5645_IN1_CTRL1 0x0a
24 #define RT5645_IN1_CTRL2 0x0
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H A Drt5640.h18 #define RT5640_RESET 0x00
19 #define RT5640_VENDOR_ID 0xfd
20 #define RT5640_VENDOR_ID1 0xfe
21 #define RT5640_VENDOR_ID2 0xff
23 #define RT5640_SPK_VOL 0x01
24 #define RT5640_HP_VOL 0x02
25 #define RT5640_OUTPUT 0x03
26 #define RT5640_MONO_OUT 0x04
28 #define RT5640_IN1_IN2 0x0d
29 #define RT5640_IN3_IN4 0x0
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H A Drt5670.h13 #define RT5670_RESET 0x00
14 #define RT5670_VENDOR_ID 0xfd
15 #define RT5670_VENDOR_ID1 0xfe
16 #define RT5670_VENDOR_ID2 0xff
18 #define RT5670_HP_VOL 0x02
19 #define RT5670_LOUT1 0x03
21 #define RT5670_CJ_CTRL1 0x0a
22 #define RT5670_CJ_CTRL2 0x0b
23 #define RT5670_CJ_CTRL3 0x0c
24 #define RT5670_IN2 0x0
[all...]
H A Drt5631.h6 #define RT5631_RESET 0x00
7 #define RT5631_SPK_OUT_VOL 0x02
8 #define RT5631_HP_OUT_VOL 0x04
9 #define RT5631_MONO_AXO_1_2_VOL 0x06
10 #define RT5631_AUX_IN_VOL 0x0A
11 #define RT5631_STEREO_DAC_VOL_1 0x0C
12 #define RT5631_MIC_CTRL_1 0x0E
13 #define RT5631_STEREO_DAC_VOL_2 0x10
14 #define RT5631_ADC_CTRL_1 0x12
15 #define RT5631_ADC_REC_MIXER 0x1
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H A Drt5665.h14 #define DEVICE_ID 0x6451
17 #define RT5665_RESET 0x0000
18 #define RT5665_VENDOR_ID 0x00fd
19 #define RT5665_VENDOR_ID_1 0x00fe
20 #define RT5665_DEVICE_ID 0x00ff
22 #define RT5665_LOUT 0x0001
23 #define RT5665_HP_CTRL_1 0x0002
24 #define RT5665_HP_CTRL_2 0x0003
25 #define RT5665_MONO_OUT 0x0004
26 #define RT5665_HPL_GAIN 0x000
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H A Drt5659.h14 #define DEVICE_ID 0x6311
17 #define RT5659_RESET 0x0000
18 #define RT5659_VENDOR_ID 0x00fd
19 #define RT5659_VENDOR_ID_1 0x00fe
20 #define RT5659_DEVICE_ID 0x00ff
22 #define RT5659_SPO_VOL 0x0001
23 #define RT5659_HP_VOL 0x0002
24 #define RT5659_LOUT 0x0003
25 #define RT5659_MONO_OUT 0x0004
26 #define RT5659_HPL_GAIN 0x000
[all...]
H A Drt5660.h16 #define RT5660_RESET 0x00
17 #define RT5660_VENDOR_ID 0xfd
18 #define RT5660_VENDOR_ID1 0xfe
19 #define RT5660_VENDOR_ID2 0xff
21 #define RT5660_SPK_VOL 0x01
22 #define RT5660_LOUT_VOL 0x02
24 #define RT5660_IN1_IN2 0x0d
25 #define RT5660_IN3_IN4 0x0e
27 #define RT5660_DAC1_DIG_VOL 0x19
28 #define RT5660_STO1_ADC_DIG_VOL 0x1
[all...]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
[all...]
/linux/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x002
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/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x002
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/linux/drivers/soc/samsung/
H A Dexynos3250-pmu.c16 { EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
17 { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
18 { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
19 { EXYNOS3_ARM_CORE1_SYS_PWR_REG, { 0x
[all...]
H A Dexynos4-pmu.c15 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
16 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
17 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
18 { S5P_ARM_CORE1_LOWPWR, { 0x
[all...]
H A Dexynos5250-pmu.c16 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
17 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
18 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
19 { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x
[all...]
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_hsi.h89 LL2_OK = 0,
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
148 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
149 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
189 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
192 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
277 CORE_RX_PKT_SOURCE_NETWORK = 0,
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_enum.h28 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
32 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
36 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x
[all...]
H A Ddce_11_0_enum.h28 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
32 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
36 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x
[all...]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.h12 #define ANALOGIX_DP_TX_SW_RESET 0x14
13 #define ANALOGIX_DP_FUNC_EN_1 0x18
14 #define ANALOGIX_DP_FUNC_EN_2 0x1C
15 #define ANALOGIX_DP_VIDEO_CTL_1 0x20
16 #define ANALOGIX_DP_VIDEO_CTL_2 0x24
17 #define ANALOGIX_DP_VIDEO_CTL_3 0x28
19 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C
20 #define ANALOGIX_DP_VIDEO_CTL_10 0x44
22 #define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8
24 #define ANALOGIX_DP_PLL_REG_1 0xf
[all...]
/linux/drivers/gpu/drm/radeon/
H A Dr100d.h31 #define CP_PACKET0 0x00000000
32 #define PACKET0_BASE_INDEX_SHIFT 0
33 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
35 #define PACKET0_COUNT_MASK (0x3fff << 16)
36 #define CP_PACKET1 0x40000000
37 #define CP_PACKET2 0x80000000
38 #define PACKET2_PAD_SHIFT 0
39 #define PACKET2_PAD_MASK (0x3fffffff << 0)
[all...]
H A Drs600d.h32 #define R_000040_GEN_INT_CNTL 0x000040
33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18)
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1)
35 #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19)
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1)
[all...]
H A Dr420d.h31 #define R_0001F8_MC_IND_INDEX 0x0001F8
32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0)
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F)
34 #define C_0001F8_MC_IND_ADDR 0xFFFFFF80
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8)
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1)
[all...]
/linux/drivers/infiniband/hw/qedr/
H A Dqedr_hsi_rdma.h50 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1
51 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0
52 #define RDMA_CQE_RESPONDER_TYPE_MASK 0x3
54 #define RDMA_CQE_RESPONDER_INV_FLG_MASK 0x1
56 #define RDMA_CQE_RESPONDER_IMM_FLG_MASK 0x1
58 #define RDMA_CQE_RESPONDER_RDMA_FLG_MASK 0x1
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