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/linux-6.8/Documentation/devicetree/bindings/soc/qcom/
Dqcom-stats.yaml59 reg = <0x0c3f0000 0x400>;
65 reg = <0x04690000 0x10000>;
/linux-6.8/arch/arm64/boot/dts/qcom/
Dsa8775p.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
41 reg = <0x0 0x0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x200>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8350.dtsi37 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #size-cells = <0>;
53 CPU0: cpu@0 {
56 reg = <0x0 0x0>;
57 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 CPU0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi32 #clock-cells = <0>;
39 #clock-cells = <0>;
47 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8650.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
48 #clock-cells = <0>;
57 #clock-cells = <0>;
66 #clock-cells = <0>;
72 #size-cells = <0>;
74 CPU0: cpu@0 {
77 reg = <0 0>;
79 clocks = <&cpufreq_hw 0>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
78 clocks = <&cpufreq_hw 0>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #size-cells = <0>;
72 CPU0: cpu@0 {
75 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8250.dtsi82 #clock-cells = <0>;
90 #clock-cells = <0>;
96 #size-cells = <0>;
98 CPU0: cpu@0 {
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
117 cache-size = <0x20000>;
123 cache-size = <0x400000>;
[all …]
Dsc7280.dtsi80 #clock-cells = <0>;
86 #clock-cells = <0>;
97 reg = <0x0 0x004cd000 0x0 0x1000>;
101 reg = <0x0 0x80000000 0x0 0x600000>;
106 reg = <0x0 0x80600000 0x0 0x200000>;
111 reg = <0x0 0x80800000 0x0 0x60000>;
116 reg = <0x0 0x80860000 0x0 0x20000>;
122 reg = <0x0 0x80884000 0x0 0x10000>;
127 reg = <0x0 0x808ff000 0x0 0x1000>;
132 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]