Home
last modified time | relevance | path

Searched +full:0 +full:x0c265000 (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/thermal/
H A Dthermal-sensor.yaml35 0 on sensor nodes with only a single sensor and at least 1 on nodes
37 enum: [0, 1]
57 reg = <0 0x0c263000 0 0x1ff>, /* TM */
58 <0 0x0c222000 0 0x1ff>; /* SROT */
68 reg = <0 0x0c265000 0 0x1ff>, /* TM */
69 <0 0x0c223000 0 0x1ff>; /* SROT */
H A Dthermal-zones.yaml68 checking this thermal zone. Setting this to 0 disables the polling
77 this to 0 disables the polling timers setup by the thermal
133 "^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$":
253 reg = <0 0x0c263000 0 0x1ff>, /* TM */
254 <0 0x0c222000 0 0x1ff>; /* SROT */
264 reg = <0 0x0c265000 0 0x1ff>, /* TM */
265 <0 0x0c223000 0 0x1ff>; /* SROT */
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6350.dtsi35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
90 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 cpu0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
H A Dsc7280.dtsi83 #clock-cells = <0>;
89 #clock-cells = <0>;
100 reg = <0x0 0x004cd000 0x0 0x1000>;
104 reg = <0x0 0x80000000 0x0 0x600000>;
109 reg = <0x0 0x80600000 0x0 0x200000>;
114 reg = <0x0 0x80800000 0x0 0x60000>;
119 reg = <0x0 0x80860000 0x0 0x20000>;
125 reg = <0x0 0x80884000 0x0 0x10000>;
130 reg = <0x0 0x808ff000 0x0 0x1000>;
135 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]