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/linux-6.8/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-14nm.yaml63 reg = <0x0ae94400 0x200>,
64 <0x0ae94600 0x280>,
65 <0x0ae94a00 0x1e0>;
71 #phy-cells = <0>;
Ddsi-phy-10nm.yaml82 reg = <0x0ae94400 0x200>,
83 <0x0ae94600 0x280>,
84 <0x0ae94a00 0x1e0>;
90 #phy-cells = <0>;
97 qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98 qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
Dqcom,sm6350-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x0ae00000 0x1000>;
100 iommus = <&apps_smmu 0x800 0x2>;
107 reg = <0x0ae01000 0x8f000>,
108 <0x0aeb0000 0x2008>;
130 interrupts = <0>;
136 #size-cells = <0>;
138 port@0 {
[all …]
Dqcom,sdm670-mdss.yaml42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
103 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
104 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
107 iommus = <&apps_smmu 0x880 0x8>,
108 <&apps_smmu 0xc80 0x8>;
116 reg = <0x0ae01000 0x8f000>,
[all …]
Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
[all …]
Dqcom,sc7180-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
101 reg = <0xae00000 0x1000>;
118 iommus = <&apps_smmu 0x800 0x2>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
138 interrupts = <0>;
144 #size-cells = <0>;
[all …]
/linux-6.8/arch/arm64/boot/dts/qcom/
Dsdm670.dtsi33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
87 reg = <0x0 0x200>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x300>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 CPU0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]