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/linux-6.8/Documentation/devicetree/bindings/remoteproc/
Dqcom,glink-edge.yaml84 reg = <0x08a00000 0x10000>;
Dqcom,sc7280-wpss-pil.yaml162 reg = <0x08a00000 0x10000>;
165 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
188 qcom,smem-states = <&wpss_smp2p_out 0>;
195 qcom,halt-regs = <&tcsr_mutex 0x37000>;
/linux-6.8/Documentation/devicetree/bindings/media/
Dstih407-c8sectpfe.txt30 - pinctrl-0 : phandle referencing pin configuration for this tsin configuration
36 - tsin-num : tsin id of the InputBlock (must be between 0 to 6)
55 reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
59 pinctrl-0 = <&pinctrl_tsin0_serial>;
73 tsin0: port@0 {
74 tsin-num = <0>;
/linux-6.8/arch/arm/boot/dts/st/
Dstihxxx-b2120.dtsi28 #size-cells = <0>;
30 simple-audio-card,dai-link@0 {
31 reg = <0>;
69 sound-dai = <&sti_sasg_codec 0>;
101 st,i2c-min-scl-pulse-width-us = <0>;
108 st,i2c-min-scl-pulse-width-us = <0>;
138 st,i2c-min-scl-pulse-width-us = <0>;
150 fixed-link = <0 1 1000 0 0>;
156 reg = <0x08a20000 0x10000>,
157 <0x08a00000 0x4000>;
[all …]
/linux-6.8/arch/arm64/boot/dts/qcom/
Dipq5018.dtsi21 #clock-cells = <0>;
26 #clock-cells = <0>;
32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0>;
47 reg = <0x1>;
57 cache-size = <0x80000>;
89 reg = <0x0 0x40000000 0x0 0x0>;
108 reg = <0x0 0x4a800000 0x0 0x200000>;
113 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]
Dipq5332.dtsi20 #clock-cells = <0>;
25 #clock-cells = <0>;
31 #size-cells = <0>;
33 CPU0: cpu@0 {
36 reg = <0x0>;
46 reg = <0x1>;
56 reg = <0x2>;
66 reg = <0x3>;
83 qcom,dload-mode = <&tcsr 0x6100>;
90 reg = <0x0 0x40000000 0x0 0x0>;
[all …]
Dipq6018.dtsi22 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 CPU0: cpu@0 {
39 reg = <0x0>;
52 reg = <0x1>;
64 reg = <0x2>;
76 reg = <0x3>;
94 qcom,dload-mode = <&tcsr 0x6100>;
106 opp-supported-hw = <0xf>;
[all …]
Dsc7280.dtsi80 #clock-cells = <0>;
86 #clock-cells = <0>;
97 reg = <0x0 0x004cd000 0x0 0x1000>;
101 reg = <0x0 0x80000000 0x0 0x600000>;
106 reg = <0x0 0x80600000 0x0 0x200000>;
111 reg = <0x0 0x80800000 0x0 0x60000>;
116 reg = <0x0 0x80860000 0x0 0x20000>;
122 reg = <0x0 0x80884000 0x0 0x10000>;
127 reg = <0x0 0x808ff000 0x0 0x1000>;
132 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]