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/qemu/include/hw/s390x/
H A Debcdic.h17 0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F,
18 0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
19 0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07,
20 0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
21 0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B,
22 0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07,
23 0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04,
24 0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A,
25 0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86,
26 0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21,
[all …]
/qemu/ebpf/
H A Drss.bpf.skeleton.h146 s->maps[0].name = "tap_rss_map_configurations"; in rss_bpf__create_skeleton()
147 s->maps[0].map = &obj->maps.tap_rss_map_configurations; in rss_bpf__create_skeleton()
164 s->progs[0].name = "tun_rss_steering_prog"; in rss_bpf__create_skeleton()
165 s->progs[0].prog = &obj->progs.tun_rss_steering_prog; in rss_bpf__create_skeleton()
166 s->progs[0].link = &obj->links.tun_rss_steering_prog; in rss_bpf__create_skeleton()
171 return 0; in rss_bpf__create_skeleton()
180 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
181 \0\0\0\0\0\0\0\0\0\0\0\xb0\x4b\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\ in rss_bpf__elf_bytes()
182 \x01\0\x7b\x1a\x48\xff\0\0\0\0\xb7\x09\0\0\0\0\0\0\x63\x9a\x54\xff\0\0\0\0\xbf\ in rss_bpf__elf_bytes()
183 \xa7\0\0\0\0\0\0\x07\x07\0\0\x54\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
[all …]
/qemu/tests/qtest/migration/s390x/
H A Da-b-bios.h7 0x7f, 0x45, 0x4c, 0x46, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x16, 0x00, 0x00, 0x00, 0x01,
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa8, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x80,
11 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38, 0x00, 0x07, 0x00, 0x40,
12 0x00, 0x0d, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04,
13 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00,
14 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
15 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x00, 0x01, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
[all …]
/qemu/tests/unit/
H A Dtest-crypto-afsplit.c43 "\x00\x01\x02\x03\x04\x05\x06\x07"
49 "\x70\xde\xfa\x07\xc5\xac\x58\xd2"
75 "\x00\x01\x02\x03\x04\x05\x06\x07"
84 "\x00\x01\x02\x03\x04\x05\x06\x07"
95 "\x00\x01\x02\x03\x04\x05\x06\x07"
97 "\x00\x01\x02\x03\x04\x05\x06\x07"
99 "\x00\x01\x02\x03\x04\x05\x06\x07"
101 "\x00\x01\x02\x03\x04\x05\x06\x07"
110 return '0' + i; in hex()
121 for (i = 0; i < len; i++) { in hex_string()
[all …]
H A Dtest-crypto-ivgen.c40 .sector = 0x1,
49 .sector = 0x1f2e3d4cULL,
58 .sector = 0x1f2e3d4c5b6a7988ULL,
67 .sector = 0x1,
76 .sector = 0x1f2e3d4cULL,
85 .sector = 0x1f2e3d4c5b6a7988ULL,
94 .sector = 0x1,
98 .key = (const uint8_t *)"\x00\x01\x02\x03\x04\x05\x06\x07"
108 .sector = 0x1f2e3d4cULL,
112 .key = (const uint8_t *)"\x00\x01\x02\x03\x04\x05\x06\x07"
[all …]
H A Dtest-crypto-der.c27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
30 "\x00\xb9\xe1\x22\xdb\x56\x2f\xb6\xf7\xf0\x0a\x87\x43\x07\x12\xdb"
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
92 "\xa3\xa2\xb1\x40\xcf\x07\x7a\x83\xae\xea\x00\xea\x74\xc7\x54\x6a"
137 "\xab\xf3\xe1\xe5\x40\x05\xed\x97\x3d\xd1\x82\x6e\x07\x02\xc0\x8f"
151 "\x30\x53" /* SEQUENCE, offset 0, length 83 */
159 "\x17\x9d\xb2\x36\x22\xcc\x07\xb3\x6d\x3c\x4e\x04\x5f\xeb\xb6\x52"
164 "\x30\x77" /* SEQUENCE, offset 0, length 119 */
169 "\xa0\x0a" /* CONTEXT SPECIFIC 0, offset 39, length 10 */
171 "\x2a\x86\x48\xce\x3d\x03\x01\x07"
[all …]
H A Dtest-crypto-akcipher.c29 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
30 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
31 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
32 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
33 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
34 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
35 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
36 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
37 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
38 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
/qemu/hw/misc/
H A Daxp2xx.c43 #define NR_REGS (0xff)
62 #define AXP209_CHIP_VERSION_ID (0x01)
63 #define AXP209_DC_DC2_OUT_V_CTRL_RESET (0x16)
68 memset(s->regs, 0, NR_REGS); in axp209_reset_enter()
69 s->ptr = 0; in axp209_reset_enter()
70 s->count = 0; in axp209_reset_enter()
72 s->regs[0x03] = AXP209_CHIP_VERSION_ID; in axp209_reset_enter()
73 s->regs[0x23] = AXP209_DC_DC2_OUT_V_CTRL_RESET; in axp209_reset_enter()
75 s->regs[0x30] = 0x60; in axp209_reset_enter()
76 s->regs[0x32] = 0x46; in axp209_reset_enter()
[all …]
/qemu/hw/display/
H A Dcirrus_vga_rop2.h34 } while (0)
53 int skipleft = s->vga.gr[0x2f] & 0x1f; in glue()
55 int skipleft = (s->vga.gr[0x2f] & 0x07) * (DEPTH / 8); in glue()
66 for(y = 0; y < bltheight; y++) { in glue()
112 int dstskipleft = s->vga.gr[0x2f] & 0x1f; in glue()
115 int srcskipleft = s->vga.gr[0x2f] & 0x07; in glue()
120 bits_xor = 0xff; in glue()
123 bits_xor = 0x00; in glue()
127 for(y = 0; y < bltheight; y++) { in glue()
128 bitmask = 0x80 >> srcskipleft; in glue()
[all …]
H A Dvga_regs.h32 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
33 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
34 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
35 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
36 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
37 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
38 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */
39 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
40 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */
41 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
[all …]
/qemu/target/tricore/
H A Dtricore-opcodes.h34 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
290 OPCM_16_SR_SYSTEM = 0x00,
291 OPCM_16_SR_ACCU = 0x32,
293 OPC1_16_SRC_ADD = 0xc2,
294 OPC1_16_SRC_ADD_A15 = 0x92,
295 OPC1_16_SRC_ADD_15A = 0x9a,
296 OPC1_16_SRR_ADD = 0x42,
297 OPC1_16_SRR_ADD_A15 = 0x12,
298 OPC1_16_SRR_ADD_15A = 0x1a,
299 OPC1_16_SRC_ADD_A = 0xb0,
[all …]
/qemu/pc-bios/keymaps/
H A Dsl3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
17 Super_L 0xdb
[all …]
/qemu/include/scsi/
H A Dconstants.h30 #define TEST_UNIT_READY 0x00
31 #define REWIND 0x01
32 #define REQUEST_SENSE 0x03
33 #define FORMAT_UNIT 0x04
34 #define READ_BLOCK_LIMITS 0x05
35 #define INITIALIZE_ELEMENT_STATUS 0x07
36 #define REASSIGN_BLOCKS 0x07
37 #define READ_6 0x08
38 #define WRITE_6 0x0a
39 #define SET_CAPACITY 0x0b
[all …]
/qemu/target/ppc/translate/
H A Dspe-ops.c.inc1 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
2 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
3 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
4 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
7 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
8 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
12 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
[all …]
H A Dvsx-ops.c.inc1 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
5 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
7 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9 GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
[all …]
/qemu/tests/bench/
H A Dtest_akcipher_keys.c.inc12 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
13 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
14 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
15 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
16 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
17 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
18 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
19 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
20 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
21 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
/qemu/include/hw/scsi/
H A Desp.h83 #define ESP_TCLO 0x0
84 #define ESP_TCMID 0x1
85 #define ESP_FIFO 0x2
86 #define ESP_CMD 0x3
87 #define ESP_RSTAT 0x4
88 #define ESP_WBUSID 0x4
89 #define ESP_RINTR 0x5
90 #define ESP_WSEL 0x5
91 #define ESP_RSEQ 0x6
92 #define ESP_WSYNTP 0x6
[all …]
/qemu/tests/functional/acpi-bits/bits-tests/
H A Dsmbios.py249 address = 0xF0000
50 mem = bits.memory(0xF0000, 0x10000)
51 for offset in range(0, len(mem), 16):
55 csum = sum(map(ord, mem[offset:offset + entry_point_length])) & 0xff
56 if csum == 0:
66 sm._header_memory = bits.memory(sm_ptr, 0x1f)
161 if i == 0:
170 smbios_structure_type = 0
186 characteristic_bytes = self.length - 0x12
211 if self.length > 0x8:
[all …]
/qemu/hw/usb/
H A Ddev-audio.c43 #define USBAUDIO_VENDOR_NUM 0x46f4 /* CRC16() of "QEMU" */
44 #define USBAUDIO_PRODUCT_NUM 0x0002
93 * block diagrams. Alternative setting 0 is always the null block diagram,
97 ALTSET_OFF = 0x00, /* No endpoint */
98 ALTSET_STEREO = 0x01, /* Single endpoint */
99 ALTSET_51 = 0x02,
100 ALTSET_71 = 0x03,
109 #define U16(x) ((x) & 0xff), (((x) >> 8) & 0xff)
110 #define U24(x) U16(x), (((x) >> 16) & 0xff)
111 #define U32(x) U24(x), (((x) >> 24) & 0xff)
[all …]
/qemu/hw/isa/
H A Dpc87312.c36 #define REG_FER 0
40 #define FER_PARALLEL_EN 0x01
41 #define FER_UART1_EN 0x02
42 #define FER_UART2_EN 0x04
43 #define FER_FDC_EN 0x08
44 #define FER_FDC_4 0x10
45 #define FER_FDC_ADDR 0x20
46 #define FER_IDE_EN 0x40
47 #define FER_IDE_ADDR 0x80
49 #define FAR_PARALLEL_ADDR 0x03
[all …]
/qemu/hw/sensor/
H A Ddps310.c17 #define NUM_REGISTERS 0x33
34 #define DPS310_PRS_B2 0x00
35 #define DPS310_PRS_B1 0x01
36 #define DPS310_PRS_B0 0x02
37 #define DPS310_TMP_B2 0x03
38 #define DPS310_TMP_B1 0x04
39 #define DPS310_TMP_B0 0x05
40 #define DPS310_PRS_CFG 0x06
41 #define DPS310_TMP_CFG 0x07
42 #define DPS310_TMP_RATE_BITS (0x70)
[all …]
/qemu/include/hw/sensor/
H A Demc141x_regs.h15 #define EMC1413_DEVICE_ID 0x21
16 #define EMC1414_DEVICE_ID 0x25
17 #define MANUFACTURER_ID 0x5d
18 #define REVISION 0x04
21 #define EMC141X_TEMP_HIGH0 0x00
22 #define EMC141X_TEMP_HIGH1 0x01
23 #define EMC141X_TEMP_HIGH2 0x23
24 #define EMC141X_TEMP_HIGH3 0x2a
25 #define EMC141X_TEMP_MAX_HIGH0 0x05
26 #define EMC141X_TEMP_MIN_HIGH0 0x06
[all …]
/qemu/tests/tcg/multiarch/
H A Dnop_func.h11 0xc0, 0x03, 0x5f, 0xd6, /* ret */
13 0x01, 0x80, 0xFA, 0x6B, /* ret */
15 0x1e, 0xff, 0x2f, 0xe1, /* bx lr */
17 0x67, 0x80, 0x00, 0x00, /* ret */
19 0x07, 0xfe, /* br %r14 */
21 0xc3, /* ret */
/qemu/tests/tcg/multiarch/arm-compat-semi/
H A Dsemiconsole.c10 #define SYS_READC 0x07
24 c = __semi_call(SYS_READC, 0); in main()
28 return 0; in main()
/qemu/tests/qtest/
H A Dfuzz-lsi53c895a-test.c25 qtest_outl(s, 0xcf8, 0x80000804); /* PCI Command Register */ in test_lsi_dma_reentrancy()
26 qtest_outw(s, 0xcfc, 0x7); /* Enables accesses */ in test_lsi_dma_reentrancy()
27 qtest_outl(s, 0xcf8, 0x80000814); /* Memory Bar 1 */ in test_lsi_dma_reentrancy()
28 qtest_outl(s, 0xcfc, 0xff100000); /* Set MMIO Address*/ in test_lsi_dma_reentrancy()
29 qtest_outl(s, 0xcf8, 0x80000818); /* Memory Bar 2 */ in test_lsi_dma_reentrancy()
30 qtest_outl(s, 0xcfc, 0xff000000); /* Set RAM Address*/ in test_lsi_dma_reentrancy()
31 qtest_writel(s, 0xff000000, 0xc0000024); in test_lsi_dma_reentrancy()
32 qtest_writel(s, 0xff000114, 0x00000080); in test_lsi_dma_reentrancy()
33 qtest_writel(s, 0xff00012c, 0xff000000); in test_lsi_dma_reentrancy()
34 qtest_writel(s, 0xff000004, 0xff000114); in test_lsi_dma_reentrancy()
[all …]

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