Searched +full:0 +full:x02200000 (Results 1 – 9 of 9) sorted by relevance
14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)[all …]
16 #define BAST_CPLD_CTRL1_LRCOFF (0x00)17 #define BAST_CPLD_CTRL1_LRCADC (0x01)18 #define BAST_CPLD_CTRL1_LRCDAC (0x02)19 #define BAST_CPLD_CTRL1_LRCARM (0x03)20 #define BAST_CPLD_CTRL1_LRMASK (0x03)24 #define BAST_CPLD_CTRL2_WNAND (0x04)25 #define BAST_CPLD_CTLR2_IDERST (0x08)29 #define BAST_CPLD_CTRL3_IDMASK (0x0e)30 #define BAST_CPLD_CTRL3_ROMWEN (0x01)34 #define BAST_CPLD_CTRL4_LLAT (0x01)[all …]
77 reg = <0x02200000 0x4000>;78 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
58 reg = <0x02200000 0x100000>;63 reg = <0x02280000 0x4000>;73 reg = <0x02284000 0x4000>;80 reg = <0x02290000 0x4000>;86 reg = <0x02288000 0x4000>;
17 #size-cells = <0>;19 cpu0: cpu@0 {22 reg = <0>;165 reg = <0x00900000 0x40000>;173 #size-cells = <0>;175 reg = <0x02018000 0x4000>;176 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;189 reg = <0x02200000 0x4000>;190 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;200 reg = <0x02204000 0x4000>;[all …]
48 #size-cells = <0>;50 cpu@0 {53 reg = <0x0>;85 #clock-cells = <0>;91 #clock-cells = <0>;99 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;104 #phy-cells = <0>;116 reg = <0x00900000 0x20000>;124 reg = <0x00a01000 0x1000>,125 <0x00a00100 0x100>;[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;97 #clock-cells = <0>;104 #clock-cells = <0>;111 #clock-cells = <0>;112 clock-frequency = <0>;118 #clock-cells = <0>;119 clock-frequency = <0>;125 #clock-cells = <0>;[all …]
12 #define ARM_R0 029 #define ARM_COND_EQ 0x0 /* == */30 #define ARM_COND_NE 0x1 /* != */31 #define ARM_COND_CS 0x2 /* unsigned >= */33 #define ARM_COND_CC 0x3 /* unsigned < */35 #define ARM_COND_MI 0x4 /* < 0 */36 #define ARM_COND_PL 0x5 /* >= 0 */37 #define ARM_COND_VS 0x6 /* Signed Overflow */38 #define ARM_COND_VC 0x7 /* No Signed Overflow */39 #define ARM_COND_HI 0x8 /* unsigned > */[all …]
32 #define MEM_PART_SYSTEM 038 QE_CLK_NONE = 0,136 return 0; in cpm_muram_dma()228 return 0; in qe_alive_during_sleep()287 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */300 __be32 traps[16]; /* Trap addresses, 0 == ignore */344 #define BD_STATUS_MASK 0xffff0000345 #define BD_LENGTH_MASK 0x0000ffff353 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */354 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */[all …]