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/linux/arch/arm/include/debug/
H A Dimx-uart.h9 #define IMX1_UART1_BASE_ADDR 0x00206000
10 #define IMX1_UART2_BASE_ADDR 0x00207000
14 #define IMX25_UART1_BASE_ADDR 0x43f90000
15 #define IMX25_UART2_BASE_ADDR 0x43f94000
16 #define IMX25_UART3_BASE_ADDR 0x5000c000
17 #define IMX25_UART4_BASE_ADDR 0x50008000
18 #define IMX25_UART5_BASE_ADDR 0x5002c000
22 #define IMX27_UART1_BASE_ADDR 0x1000a000
23 #define IMX27_UART2_BASE_ADDR 0x1000b000
24 #define IMX27_UART3_BASE_ADDR 0x1000c000
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
79 reg = <0x101c0000 0xb00>;
96 reg = <0x101d0000 0x100>;
102 reg = <0x12d10000 0x100>;
111 reg = <0x12ca0000 0x1000>;
[all …]
H A Dexynos4210.dtsi178 #size-cells = <0>;
194 reg = <0x900>;
213 reg = <0x901>;
230 bus_leftbus_opp_table: opp-table-0 {
249 reg = <0x02020000 0x20000>;
252 ranges = <0 0x02020000 0x20000>;
254 smp-sram@0 {
256 reg = <0x0 0x1000>;
261 reg = <0x1f000 0x1000>;
267 reg = <0x10023ca0 0x20>;
[all …]
H A Dexynos3250.dtsi199 #size-cells = <0>;
212 cpu0: cpu@0 {
215 reg = <0>;
259 xusbxti: clock-0 {
261 clock-frequency = <0>;
262 #clock-cells = <0>;
268 clock-frequency = <0>;
269 #clock-cells = <0>;
275 clock-frequency = <0>;
276 #clock-cells = <0>;
[all …]
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da2xx_catalog.c13 .chip_ids = ADRENO_CHIP_IDS(0x02000000),
24 .chip_ids = ADRENO_CHIP_IDS(0x02000001),
35 .chip_ids = ADRENO_CHIP_IDS(0x02020000),
/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml165 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
169 ranges = <0 0x5c000000 0x40000>;
172 reg = <0x100 0x50>;
176 reg = <0x1000 0x1000>;
181 reg = <0x20000 0x20000>;
196 reg = <0x02020000 0x54000>;
199 ranges = <0 0x02020000 0x54000>;
201 smp-sram@0 {
203 reg = <0x0 0x1000>;
208 reg = <0x53000 0x1000>;
[all …]
/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
24 cpu@0 {
27 reg = <0x0 0x0>;
34 reg = <0x0 0x1>;
41 reg = <0x0 0x2>;
48 reg = <0x0 0x3>;
66 reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
67 <0x04 0x01000000 0x0 0x1000000>; /* GICR */
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
[all …]
/linux/net/smc/
H A Dsmc_clc.h22 #define SMC_CLC_PROPOSAL 0x01
23 #define SMC_CLC_ACCEPT 0x02
24 #define SMC_CLC_CONFIRM 0x03
25 #define SMC_CLC_DECLINE 0x04
27 #define SMC_TYPE_R 0 /* SMC-R only */
33 #define SMC_CLC_DECL_MEM 0x01010000 /* insufficient memory resources */
34 #define SMC_CLC_DECL_TIMEOUT_CL 0x02010000 /* timeout w4 QP confirm link */
35 #define SMC_CLC_DECL_TIMEOUT_AL 0x02020000 /* timeout w4 QP add link */
36 #define SMC_CLC_DECL_CNFERR 0x03000000 /* configuration error */
37 #define SMC_CLC_DECL_PEERNOSMC 0x03010000 /* peer did not indicate SMC */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sl.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
86 #clock-cells = <0>;
92 #clock-cells = <0>;
100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
105 #phy-cells = <0>;
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
128 reg = <0x00a01000 0x1000>,
[all …]
H A Dimx6ul.dtsi58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
108 #clock-cells = <0>;
115 #clock-cells = <0>;
122 #clock-cells = <0>;
123 clock-frequency = <0>;
129 #clock-cells = <0>;
130 clock-frequency = <0>;
149 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6qdl.dtsi59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
[all …]
H A Dimx6sx.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
[all …]
/linux/drivers/media/pci/pt1/
H A Dpt1.c131 I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x1b),
134 I2C_BOARD_INFO("qm1d1b0004", 0x60),
139 I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x1a),
142 I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
147 I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x19),
150 I2C_BOARD_INFO("qm1d1b0004", 0x60),
155 I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x18),
158 I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
164 {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01},
165 {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0},
[all …]
/linux/drivers/scsi/megaraid/
H A Dmegaraid_sas.h34 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
35 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
36 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
37 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
38 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
39 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
40 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
41 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
42 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
43 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
[all …]
/linux/sound/pci/ca0106/
H A Dca0106_main.c77 * Add 4 capture channels. (SPDIF only comes in on channel 0. )
164 { .serial = 0x10131102,
182 { .serial = 0x10121102,
188 { .serial = 0x10021102,
192 { .serial = 0x10051102,
196 { .serial = 0x10061102,
201 { .serial = 0x10071102,
211 { .serial = 0x100a1102,
215 .spi_dac = 0x4021 } ,
222 { .serial = 0x10111102,
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
H A Dk3-j784s4-j742s2-main-common.dtsi16 #clock-cells = <0>;
30 reg = <0x00 0x70000000 0x00 0x800000>;
33 ranges = <0x00 0x00 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x00 0x20000>;
40 reg = <0x1f0000 0x10000>;
44 reg = <0x200000 0x200000>;
50 reg = <0x00 0x00100000 0x00 0x1c000>;
53 ranges = <0x00 0x00 0x00100000 0x1c000>;
57 reg = <0x4034 0x4>;
[all …]