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/linux-5.10/arch/arm/include/debug/
Dimx-uart.h9 #define IMX1_UART1_BASE_ADDR 0x00206000
10 #define IMX1_UART2_BASE_ADDR 0x00207000
14 #define IMX21_UART1_BASE_ADDR 0x1000a000
15 #define IMX21_UART2_BASE_ADDR 0x1000b000
16 #define IMX21_UART3_BASE_ADDR 0x1000c000
17 #define IMX21_UART4_BASE_ADDR 0x1000d000
21 #define IMX25_UART1_BASE_ADDR 0x43f90000
22 #define IMX25_UART2_BASE_ADDR 0x43f94000
23 #define IMX25_UART3_BASE_ADDR 0x5000c000
24 #define IMX25_UART4_BASE_ADDR 0x50008000
[all …]
/linux-5.10/arch/arm/boot/dts/
Dexynos54xx.dtsi42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
78 reg = <0x101c0000 0xb00>;
95 reg = <0x101d0000 0x100>;
101 reg = <0x12d10000 0x100>;
111 reg = <0x12ca0000 0x1000>;
[all …]
Dexynos4210.dtsi33 #size-cells = <0>;
38 reg = <0x900>;
57 reg = <0x901>;
77 reg = <0x02020000 0x20000>;
80 ranges = <0 0x02020000 0x20000>;
82 smp-sram@0 {
84 reg = <0x0 0x1000>;
89 reg = <0x1f000 0x1000>;
95 reg = <0x10023CA0 0x20>;
96 #power-domain-cells = <0>;
[all …]
Dexynos4412.dtsi36 #size-cells = <0>;
41 reg = <0xA00>;
51 reg = <0xA01>;
61 reg = <0xA02>;
71 reg = <0xA03>;
162 reg = <0x11400000 0x1000>;
168 reg = <0x11000000 0x1000>;
180 reg = <0x03860000 0x1000>;
182 interrupts = <10 0>;
187 reg = <0x106E0000 0x1000>;
[all …]
Dexynos3250.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0>;
100 xusbxti: clock-0 {
102 clock-frequency = <0>;
103 #clock-cells = <0>;
109 clock-frequency = <0>;
110 #clock-cells = <0>;
116 clock-frequency = <0>;
117 #clock-cells = <0>;
[all …]
Dexynos5250.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0>;
169 reg = <0x02020000 0x30000>;
172 ranges = <0 0x02020000 0x30000>;
174 smp-sram@0 {
176 reg = <0x0 0x1000>;
181 reg = <0x2f000 0x1000>;
187 reg = <0x10044000 0x20>;
188 #power-domain-cells = <0>;
[all …]
Dimx6sll.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
97 clock-frequency = <0>;
103 #clock-cells = <0>;
104 clock-frequency = <0>;
117 reg = <0x00900000 0x20000>;
[all …]
Dimx6sl.dtsi48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0x0>;
85 #clock-cells = <0>;
91 #clock-cells = <0>;
99 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
104 #phy-cells = <0>;
116 reg = <0x00900000 0x20000>;
124 reg = <0x00a01000 0x1000>,
125 <0x00a00100 0x100>;
[all …]
Dimx6ul.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
108 #clock-cells = <0>;
115 #clock-cells = <0>;
122 #clock-cells = <0>;
123 clock-frequency = <0>;
129 #clock-cells = <0>;
130 clock-frequency = <0>;
149 reg = <0x00900000 0x20000>;
[all …]
Dimx6qdl.dtsi55 #clock-cells = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
74 #size-cells = <0>;
79 lvds-channel@0 {
81 #size-cells = <0>;
82 reg = <0>;
85 port@0 {
86 reg = <0>;
[all …]
Dimx6sx.dtsi58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
111 #clock-cells = <0>;
112 clock-frequency = <0>;
118 #clock-cells = <0>;
119 clock-frequency = <0>;
125 #clock-cells = <0>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml143 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
147 ranges = <0 0x5c000000 0x40000>;
150 reg = <0x100 0x50>;
154 reg = <0x1000 0x1000>;
159 reg = <0x20000 0x20000>;
174 reg = <0x02020000 0x54000>;
177 ranges = <0 0x02020000 0x54000>;
179 smp-sram@0 {
181 reg = <0x0 0x1000>;
186 reg = <0x53000 0x1000>;
[all …]
/linux-5.10/arch/arm64/boot/dts/cavium/
Dthunder2-99xx.dtsi21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
24 cpu@0 {
27 reg = <0x0 0x0>;
34 reg = <0x0 0x1>;
41 reg = <0x0 0x2>;
48 reg = <0x0 0x3>;
66 reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
67 <0x04 0x01000000 0x0 0x1000000>; /* GICR */
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
[all …]
/linux-5.10/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux-5.10/net/smc/
Dsmc_clc.h20 #define SMC_CLC_PROPOSAL 0x01
21 #define SMC_CLC_ACCEPT 0x02
22 #define SMC_CLC_CONFIRM 0x03
23 #define SMC_CLC_DECLINE 0x04
25 #define SMC_TYPE_R 0 /* SMC-R only */
31 #define SMC_CLC_DECL_MEM 0x01010000 /* insufficient memory resources */
32 #define SMC_CLC_DECL_TIMEOUT_CL 0x02010000 /* timeout w4 QP confirm link */
33 #define SMC_CLC_DECL_TIMEOUT_AL 0x02020000 /* timeout w4 QP add link */
34 #define SMC_CLC_DECL_CNFERR 0x03000000 /* configuration error */
35 #define SMC_CLC_DECL_PEERNOSMC 0x03010000 /* peer did not indicate SMC */
[all …]
/linux-5.10/drivers/media/pci/pt1/
Dpt1.c131 I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x1b),
134 I2C_BOARD_INFO("qm1d1b0004", 0x60),
139 I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x1a),
142 I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
147 I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x19),
150 I2C_BOARD_INFO("qm1d1b0004", 0x60),
155 I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x18),
158 I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
164 {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01},
165 {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0},
[all …]
/linux-5.10/drivers/scsi/megaraid/
Dmegaraid_sas.h32 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
33 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
34 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
35 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
36 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
37 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
38 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
39 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
40 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
41 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
[all …]
/linux-5.10/sound/pci/ca0106/
Dca0106_main.c77 * Add 4 capture channels. (SPDIF only comes in on channel 0. )
165 { .serial = 0x10131102,
183 { .serial = 0x10121102,
189 { .serial = 0x10021102,
193 { .serial = 0x10051102,
197 { .serial = 0x10061102,
202 { .serial = 0x10071102,
212 { .serial = 0x100a1102,
216 .spi_dac = 0x4021 } ,
223 { .serial = 0x10111102,
[all …]